On TI's AM654 and J721e SoCs, certain clocks can be gated/ungated by setting a single bit in SoC's System Control registers. Sometime more than one clock control can be in the same register. But these registers might also have bits to control other SoC functionalities. For example, Time Base clock(TBclk) enable bits for various EPWM IPs are all in EPWM_CTRL Syscon registers on K2G SoC. This series adds a new clk driver to support controlling tbclk. Registers which control clocks will be grouped into a syscon DT node, thus enabling sharing of register across clk drivers and other drivers. v2: Simplify driver to have only one clock node per group of syscon controller registers instead of one per clock instance. v1: https://patchwork.kernel.org/cover/10848783/ Vignesh Raghavendra (2): dt-bindings: clock: Add binding documentation for TI syscon gate clock clk: keystone: Add new driver to handle syscon based clocks .../bindings/clock/ti,am654-ehrpwm-tbclk.yaml | 47 +++++ drivers/clk/keystone/Kconfig | 8 + drivers/clk/keystone/Makefile | 1 + drivers/clk/keystone/syscon-clk.c | 177 ++++++++++++++++++ 4 files changed, 233 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml create mode 100644 drivers/clk/keystone/syscon-clk.c -- 2.25.0
