Hi Andrew,
Thanks a lot for your comments!
> -----Original Message-----
> From: Andrew Murray <andrew.murray@xxxxxxx>
> Sent: 2020年1月13日 19:27
> To: Z.q. Hou <zhiqiang.hou@xxxxxxx>
> Cc: linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> bhelgaas@xxxxxxxxxx; robh+dt@xxxxxxxxxx; arnd@xxxxxxxx;
> mark.rutland@xxxxxxx; l.subrahmanya@xxxxxxxxxxxxxx;
> shawnguo@xxxxxxxxxx; m.karthikeyan@xxxxxxxxxxxxxx; Leo Li
> <leoyang.li@xxxxxxx>; lorenzo.pieralisi@xxxxxxx;
> catalin.marinas@xxxxxxx; will.deacon@xxxxxxx; Mingkai Hu
> <mingkai.hu@xxxxxxx>; M.h. Lian <minghuan.lian@xxxxxxx>; Xiaowei Bao
> <xiaowei.bao@xxxxxxx>
> Subject: Re: [PATCHv9 07/12] PCI: mobiveil: Make mobiveil_host_init() can be
> used to re-init host
>
> On Wed, Nov 20, 2019 at 03:46:03AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> >
> > Make the mobiveil_host_init() function can be used to re-init
>
> Perhaps reword to "Allow the mobiveil_host_init() function to be used to ...
>
Thanks a lot for your suggestion, will change in v10.
Thanks,
Zhiqiang
> > host controller's PAB and GPEX CSR register block, as NXP integrated
> > Mobiveil IP has to reset and then re-init the PAB and GPEX CSR
> > registers upon hot-reset.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@xxxxxxxxxxxxxx>
> > ---
> > V9:
> > - No change
> >
> > .../controller/mobiveil/pcie-mobiveil-host.c | 19 ++++++++++++-------
> > .../pci/controller/mobiveil/pcie-mobiveil.h | 1 +
> > 2 files changed, 13 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > index 3cd93df6fe6e..9bc3da036720 100644
> > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > @@ -221,18 +221,23 @@ static void mobiveil_pcie_enable_msi(struct
> mobiveil_pcie *pcie)
> > writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); }
> >
> > -static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> > +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
> > {
> > struct root_port *rp = &pcie->rp;
> > struct pci_host_bridge *bridge = rp->bridge;
> > u32 value, pab_ctrl, type;
> > struct resource_entry *win;
> >
> > - /* setup bus numbers */
> > - value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
> > - value &= 0xff000000;
> > - value |= 0x00ff0100;
> > - mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
> > + pcie->ib_wins_configured = 0;
> > + pcie->ob_wins_configured = 0;
>
> This works so long as the number of bridge->windows never reduces. I think
> this assumption holds true.
>
> Thanks,
>
> Andrew Murray
>
> > +
> > + if (!reinit) {
> > + /* setup bus numbers */
> > + value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
> > + value &= 0xff000000;
> > + value |= 0x00ff0100;
> > + mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
> > + }
> >
> > /*
> > * program Bus Master Enable Bit in Command Register in PAB Config
> > @@ -569,7 +574,7 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie
> *pcie)
> > * configure all inbound and outbound windows and prepare the RC for
> > * config access
> > */
> > - ret = mobiveil_host_init(pcie);
> > + ret = mobiveil_host_init(pcie, false);
> > if (ret) {
> > dev_err(dev, "Failed to initialize host\n");
> > return ret;
> > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > index 95d2e7c809b8..37116c2a19fe 100644
> > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > @@ -166,6 +166,7 @@ struct mobiveil_pcie { };
> >
> > int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
> > +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
> > bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie); int
> > mobiveil_bringup_link(struct mobiveil_pcie *pcie); void
> > program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64
> > cpu_addr,
> > --
> > 2.17.1
> >
