Quoting Sowjanya Komatineni (2020-01-28 10:23:18) > Tegra210 CSI hardware internally uses PLLD for internal test pattern > generator logic. > > PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD > out to CSI during TPG mode. > > This patch adds this CSI TPG clock gate to Tegra210 clock driver > to allow Tegra video driver to ungate CSI TPG clock during TPG mode > and gate during non TPG mode. > > Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx> > --- Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>
