On 1/31/20 7:11 AM, Dan Murphy wrote:
> Set the speed optimization bit on the DP83867 PHY.
> This feature can also be strapped on the 64 pin PHY devices
> but the 48 pin devices do not have the strap pin available to enable
> this feature in the hardware. PHY team suggests to have this bit set.
OK, but why and how does that optimization work exactly? Departing from
the BMSR reads means you possibly are going to introduce bugs and/or
incomplete information. For instance, you set phydev->pause and
phydev->asym_pause to 0 now, is there no way to extract what the link
partner has advertised?
>
> With this bit set the PHY will auto negotiate and report the link
> parameters in the PHYSTS register and not in the BMCR.
That should be BMSR, the BMCR is about control, not status.
> So we need to
> over ride the genphy_read_status with a DP83867 specific read status.
>
> Signed-off-by: Dan Murphy <dmurphy@xxxxxx>
> ---
> drivers/net/phy/dp83867.c | 48 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index 967f57ed0b65..695aaf4f942f 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -21,6 +21,7 @@
> #define DP83867_DEVADDR 0x1f
>
> #define MII_DP83867_PHYCTRL 0x10
> +#define MII_DP83867_PHYSTS 0x11
> #define MII_DP83867_MICR 0x12
> #define MII_DP83867_ISR 0x13
> #define DP83867_CFG2 0x14
> @@ -118,6 +119,15 @@
> #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
> #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
>
> +/* PHY STS bits */
> +#define DP83867_PHYSTS_1000 BIT(15)
> +#define DP83867_PHYSTS_100 BIT(14)
> +#define DP83867_PHYSTS_DUPLEX BIT(13)
> +#define DP83867_PHYSTS_LINK BIT(10)
> +
> +/* CFG2 bits */
> +#define DP83867_SPEED_OPTIMIZED_EN (BIT(8) | BIT(9))
> +
> /* CFG3 bits */
> #define DP83867_CFG3_INT_OE BIT(7)
> #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
> @@ -287,6 +297,36 @@ static int dp83867_config_intr(struct phy_device *phydev)
> return phy_write(phydev, MII_DP83867_MICR, micr_status);
> }
>
> +static int dp83867_read_status(struct phy_device *phydev)
> +{
> + int status = phy_read(phydev, MII_DP83867_PHYSTS);
> +
> + if (status < 0)
> + return status;
> +
> + if (status & DP83867_PHYSTS_DUPLEX)
> + phydev->duplex = DUPLEX_FULL;
> + else
> + phydev->duplex = DUPLEX_HALF;
> +
> + if (status & DP83867_PHYSTS_1000)
> + phydev->speed = SPEED_1000;
> + else if (status & DP83867_PHYSTS_100)
> + phydev->speed = SPEED_100;
> + else
> + phydev->speed = SPEED_10;
> +
> + if (status & DP83867_PHYSTS_LINK)
> + phydev->link = 1;
> + else
> + phydev->link = 0;
> +
> + phydev->pause = 0;
> + phydev->asym_pause = 0;
> +
> + return 0;
> +}
> +
> static int dp83867_config_port_mirroring(struct phy_device *phydev)
> {
> struct dp83867_private *dp83867 =
> @@ -467,6 +507,12 @@ static int dp83867_config_init(struct phy_device *phydev)
> int ret, val, bs;
> u16 delay;
>
> + /* Force speed optimization for the PHY even if it strapped */
> + ret = phy_modify(phydev, DP83867_CFG2, DP83867_SPEED_OPTIMIZED_EN,
> + DP83867_SPEED_OPTIMIZED_EN);
> + if (ret)
> + return ret;
> +
> ret = dp83867_verify_rgmii_cfg(phydev);
> if (ret)
> return ret;
> @@ -655,6 +701,8 @@ static struct phy_driver dp83867_driver[] = {
> .config_init = dp83867_config_init,
> .soft_reset = dp83867_phy_reset,
>
> + .read_status = dp83867_read_status,
> +
> .get_wol = dp83867_get_wol,
> .set_wol = dp83867_set_wol,
>
>
--
Florian
