Add OPP tables required to scale DDR/L3 per freq-domain on SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 287 +++++++++++++++++++++++++++
1 file changed, 287 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index ba53ddf17ee3a..699cafc1a727d 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -109,6 +109,12 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>,
+ <&cpu0_ddr_bw_opp_table>,
+ <&cpu0_l3_bw_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+ interconnect-names = "cpu-ddr", "cpu-l3";
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
@@ -129,6 +135,12 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
+ operating-points-v2 = <&cpu0_opp_table>,
+ <&cpu0_ddr_bw_opp_table>,
+ <&cpu0_l3_bw_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+ interconnect-names = "cpu-ddr", "cpu-l3";
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
@@ -145,6 +157,12 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
+ operating-points-v2 = <&cpu0_opp_table>,
+ <&cpu0_ddr_bw_opp_table>,
+ <&cpu0_l3_bw_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+ interconnect-names = "cpu-ddr", "cpu-l3";
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
@@ -161,6 +179,12 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
+ operating-points-v2 = <&cpu0_opp_table>,
+ <&cpu0_ddr_bw_opp_table>,
+ <&cpu0_l3_bw_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+ interconnect-names = "cpu-ddr", "cpu-l3";
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
@@ -177,6 +201,12 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
+ operating-points-v2 = <&cpu0_opp_table>,
+ <&cpu0_ddr_bw_opp_table>,
+ <&cpu0_l3_bw_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+ interconnect-names = "cpu-ddr", "cpu-l3";
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
@@ -193,6 +223,12 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
+ operating-points-v2 = <&cpu0_opp_table>,
+ <&cpu0_ddr_bw_opp_table>,
+ <&cpu0_l3_bw_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+ interconnect-names = "cpu-ddr", "cpu-l3";
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
@@ -209,6 +245,12 @@
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
next-level-cache = <&L2_600>;
+ operating-points-v2 = <&cpu6_opp_table>,
+ <&cpu6_ddr_bw_opp_table>,
+ <&cpu6_l3_bw_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+ interconnect-names = "cpu-ddr", "cpu-l3";
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
@@ -225,6 +267,12 @@
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <405>;
next-level-cache = <&L2_700>;
+ operating-points-v2 = <&cpu6_opp_table>,
+ <&cpu6_ddr_bw_opp_table>,
+ <&cpu6_l3_bw_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
+ interconnect-names = "cpu-ddr", "cpu-l3";
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
@@ -270,6 +318,245 @@
};
};
+ cpu0_opp_table: cpu0_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cpu0_ddr_bw_opp1>, <&cpu0_l3_bw_opp1>;
+ };
+
+ cpu0_opp2: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ required-opps = <&cpu0_ddr_bw_opp1>, <&cpu0_l3_bw_opp1>;
+ };
+
+ cpu0_opp3: opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ required-opps = <&cpu0_ddr_bw_opp1>, <&cpu0_l3_bw_opp1>;
+ };
+
+ cpu0_opp4: opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ required-opps = <&cpu0_ddr_bw_opp2>, <&cpu0_l3_bw_opp2>;
+ };
+
+ cpu0_opp5: opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ required-opps = <&cpu0_ddr_bw_opp3>, <&cpu0_l3_bw_opp3>;
+ };
+
+ cpu0_opp6: opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ required-opps = <&cpu0_ddr_bw_opp3>, <&cpu0_l3_bw_opp3>;
+ };
+
+ cpu0_opp7: opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ required-opps = <&cpu0_ddr_bw_opp4>, <&cpu0_l3_bw_opp4>;
+ };
+
+ cpu0_opp8: opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ required-opps = <&cpu0_ddr_bw_opp4>, <&cpu0_l3_bw_opp4>;
+ };
+
+ cpu0_opp9: opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ required-opps = <&cpu0_ddr_bw_opp4>, <&cpu0_l3_bw_opp4>;
+ };
+
+ cpu0_opp10: opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ required-opps = <&cpu0_ddr_bw_opp5>, <&cpu0_l3_bw_opp5>;
+ };
+ };
+
+ cpu6_opp_table: cpu6_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu6_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>;
+ };
+
+ cpu6_opp2: opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>;
+ };
+
+ cpu6_opp3: opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>;
+ };
+
+ cpu6_opp4: opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>;
+ };
+
+ cpu6_opp5: opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>;
+ };
+
+ cpu6_opp6: opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ required-opps = <&cpu6_ddr_bw_opp2>, <&cpu6_l3_bw_opp2>;
+ };
+
+ cpu6_opp7: opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ required-opps = <&cpu6_ddr_bw_opp2>, <&cpu6_l3_bw_opp3>;
+ };
+
+ cpu6_opp8: opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp4>;
+ };
+
+ cpu6_opp9: opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp4>;
+ };
+
+ cpu6_opp10: opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp5>;
+ };
+
+ cpu6_opp11: opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp5>;
+ };
+
+ cpu6_opp12: opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp5>;
+ };
+
+ cpu6_opp13: opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ required-opps = <&cpu6_ddr_bw_opp4>, <&cpu6_l3_bw_opp5>;
+ };
+
+ cpu6_opp14: opp-2323200000 {
+ opp-hz = /bits/ 64 <2323200000>;
+ required-opps = <&cpu6_ddr_bw_opp4>, <&cpu6_l3_bw_opp5>;
+ };
+
+ cpu6_opp15: opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ required-opps = <&cpu6_ddr_bw_opp5>, <&cpu6_l3_bw_opp6>;
+ };
+ };
+
+ cpu0_ddr_bw_opp_table: cpu0-ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_ddr_bw_opp1: opp-300000000 {
+ opp-peak-kBps =/bits/ 32 <1200000>;
+ };
+
+ cpu0_ddr_bw_opp2: opp-451000000 {
+ opp-peak-kBps =/bits/ 32 <1804000>;
+ };
+
+ cpu0_ddr_bw_opp3: opp-547000000 {
+ opp-peak-kBps =/bits/ 32 <2188000>;
+ };
+
+ cpu0_ddr_bw_opp4: opp-768000000 {
+ opp-peak-kBps =/bits/ 32 <3072000>;
+ };
+
+ cpu0_ddr_bw_opp5: opp-1017000000 {
+ opp-peak-kBps =/bits/ 32 <4068000>;
+ };
+ };
+
+ cpu0_l3_bw_opp_table: cpu0-l3-bw-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_l3_bw_opp1: opp-300000000 {
+ opp-peak-kBps = /bits/ 32 <4800000>;
+ };
+
+ cpu0_l3_bw_opp2: opp-556800000 {
+ opp-peak-kBps = /bits/ 32 <8908800>;
+ };
+
+ cpu0_l3_bw_opp3: opp-806400000 {
+ opp-peak-kBps = /bits/ 32 <12902400>;
+ };
+
+ cpu0_l3_bw_opp4: opp-940800000 {
+ opp-peak-kBps = /bits/ 32 <15052800>;
+ };
+
+ cpu0_l3_bw_opp5: opp-1401000000 {
+ opp-peak-kBps = /bits/ 32 <22425600>;
+ };
+ };
+
+ cpu6_ddr_bw_opp_table: cpu6-ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu6_ddr_bw_opp1: opp-547000000 {
+ opp-peak-kBps =/bits/ 32 <2188000>;
+ };
+
+ cpu6_ddr_bw_opp2: opp-1017000000 {
+ opp-peak-kBps =/bits/ 32 <4068000>;
+ };
+
+ cpu6_ddr_bw_opp3: opp-1555000000 {
+ opp-peak-kBps =/bits/ 32 <6220000>;
+ };
+
+ cpu6_ddr_bw_opp4: opp-1804000000 {
+ opp-peak-kBps =/bits/ 32 <7216000>;
+ };
+
+ cpu6_ddr_bw_opp5: opp-2133000000 {
+ opp-peak-kBps =/bits/ 32 <8532000>;
+ };
+ };
+
+ cpu6_l3_bw_opp_table: cpu6-l3-bw-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu6_l3_bw_opp1: opp-556800000 {
+ opp-peak-kBps = /bits/ 32 <8908800>;
+ };
+
+ cpu6_l3_bw_opp2: opp-806400000 {
+ opp-peak-kBps = /bits/ 32 <12902400>;
+ };
+
+ cpu6_l3_bw_opp3: opp-940800000 {
+ opp-peak-kBps = /bits/ 32 <15052800>;
+ };
+
+ cpu6_l3_bw_opp4: opp-1209600000 {
+ opp-peak-kBps = /bits/ 32 <19353600>;
+ };
+
+ cpu6_l3_bw_opp5: opp-1401000000 {
+ opp-peak-kBps = /bits/ 32 <22425600>;
+ };
+
+ cpu6_l3_bw_opp6: opp-1459000000 {
+ opp-peak-kBps = /bits/ 32 <23347200>;
+ };
+ };
+
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
--
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