Quoting Rajan Vaja (2019-12-04 22:35:58) > zynqmp_clk_divider_round_rate() returns actual divider value > after calculating from parent rate and desired rate, even though > that rate is not supported by single divider of hardware. It is > also possible that such divisor value can be achieved through 2 > different dividers. As, Linux tries to set such divisor value(out > of range) in single divider set divider is getting failed. > > Fix the same by computing best possible combination of two > divisors which provides more accurate clock rate. > > Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx> > Signed-off-by: Tejas Patel <tejas.patel@xxxxxxxxxx> > Signed-off-by: Rajan Vaja <rajan.vaja@xxxxxxxxxx> > --- Applied to clk-next
