On 1/15/2020 8:49 PM, James Morse wrote:
Hi Hanna,
(This was still on my list. I've not seen a newer version, its not in next, and it still
applies, so:)
Thank you.
On 15/10/2019 13:09, Hanna Hawa wrote:
Adds support for Amazon's Annapurna Labs L1 EDAC driver to detect and
report L1 errors.
diff --git a/drivers/edac/al_l1_edac.c b/drivers/edac/al_l1_edac.c
new file mode 100644
index 000000000000..e363a80b4d13
--- /dev/null
+++ b/drivers/edac/al_l1_edac.c
@@ -0,0 +1,190 @@
+#include <asm/sysreg.h>
+#include <linux/bitfield.h>
+#include <linux/of.h>
+#include <linux/smp.h>
You need <linux/platform_device.h> for platform_device_register_simple().
Will be added in next PS.
[...]
+static void al_l1_edac_cpumerrsr_read_status(void *arg)
+{
+ for (i = 0; i < repeat; i++) {
+ if (fatal)
+ edac_device_handle_ue(edac_dev, 0, 0, msg);
+ else
+ edac_device_handle_ce(edac_dev, 0, 0, msg);
+ }
What serialises these? You kick this off from on_each_cpu(), what stops two CPUs calling
this at the same time? 'edac_dev->counters.ce_count += count;' will go wrong in this case.
I think you need a spinlock around the edac_device_* calls that take edac_dev so that only
one occurs at a time.
Agree with you, will add spinlock in next PS.
+}
+
+static void al_l1_edac_check(struct edac_device_ctl_info *edac_dev)
+{
+ on_each_cpu(al_l1_edac_cpumerrsr_read_status, edac_dev, 1);
+}
+
+static int al_l1_edac_probe(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_dev;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ edac_dev = edac_device_alloc_ctl_info(0, DRV_NAME, 1, "L", 1, 1, NULL,
+ 0, edac_device_alloc_index());
+ if (!edac_dev)
+ return -ENOMEM;
+
+ edac_dev->edac_check = al_l1_edac_check;
+ edac_dev->dev = dev;
+ edac_dev->mod_name = DRV_NAME;
+ edac_dev->dev_name = dev_name(dev);
+ edac_dev->ctl_name = "L1_cache";
+ platform_set_drvdata(pdev, edac_dev);
+
+ ret = edac_device_add_device(edac_dev);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
(this goto has one user, meaning you can remove it by restructuring the code)
Will be fixed in next PS.
+ dev_err(dev, "Failed to add L1 edac device (%d)\n", ret);
+ edac_device_free_ctl_info(edac_dev);
+
+ return ret;
+}
+
+static const struct of_device_id al_l1_edac_of_match[] = {
+ { .compatible = "al,alpine-v2" },
+ { .compatible = "amazon,alpine-v3" },
+ {}
+};
Unusually these are machine compatibles. It may be worth a comment that these are the
platforms which are known to have Cortex-A57/A72 configured with this support, and access
to the registers enabled by firmware.
Will be added.
+MODULE_DEVICE_TABLE(of, al_l1_edac_of_match);
[..]
+static int __init al_l1_init(void)
+{
+ struct device_node *root = of_find_node_by_path("/");
+ int ret;
root could be NULL here.
Will be fixed.
+ if (!of_match_node(al_l1_edac_of_match, root))
+ return 0;
+
+ ret = platform_driver_register(&al_l1_edac_driver);
+ if (ret) {
+ pr_err("Failed to register %s (%d)\n", DRV_NAME, ret);
+ return ret;
+ }
+
+ edac_l1_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0);
+ if (IS_ERR(edac_l1_device)) {
+ pr_err("Failed to register EDAC AL L1 platform device\n");
+ return PTR_ERR(edac_l1_device);
+ }
+
+ return 0;
+}
With the edac_device_handle_ce() race fixed:
Reviewed-by: James Morse <james.morse@xxxxxxx>
Thanks,
Hanna
Thanks,
James
