On Wed, Jan 08, 2020 at 09:53:29PM +0100, Johan Jonker wrote: > Add the Rockchip NAND controller bindings. > > Signed-off-by: Johan Jonker <jbx6244@xxxxxxxxx> > --- > .../devicetree/bindings/mtd/rockchip,nandc.yaml | 78 ++++++++++++++++++++++ > 1 file changed, 78 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/rockchip,nandc.yaml > > diff --git a/Documentation/devicetree/bindings/mtd/rockchip,nandc.yaml b/Documentation/devicetree/bindings/mtd/rockchip,nandc.yaml > new file mode 100644 > index 000000000..573d1a580 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/rockchip,nandc.yaml > @@ -0,0 +1,78 @@ > +# SPDX-License-Identifier: GPL-2.0 Dual license new bindings: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mtd/rockchip,nandc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip NAND Controller Device Tree Bindings > + > +allOf: > + - $ref: "nand-controller.yaml" Should end with a '#'. > + > +maintainers: > + - Heiko Stuebner <heiko@xxxxxxxxx> > + > +properties: > + compatible: > + enum: > + - rockchip,nandc-v6 > + - rockchip,nandc-v9 Use SoC specific compatibles, not version numbers. > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + oneOf: > + - items: > + - const: hclk_nandc > + - items: > + - const: clk_nandc > + - const: hclk_nandc Can't you put hclk_nandc first so it's always index 0. > + > +patternProperties: > + "^nand@[a-f0-9]+$": > + type: object > + properties: > + reg: > + minimum: 0 > + maximum: 3 > + > + nand-is-boot-medium: true > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + > +examples: > + - | > + #include <dt-bindings/clock/rk3188-cru-common.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + nandc: nand-controller@10500000 { > + compatible = "rockchip,nandc-v6"; > + reg = <0x10500000 0x4000>; > + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru HCLK_NANDC0>; > + clock-names = "hclk_nandc"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + nand@0 { > + reg = <0>; > + nand-is-boot-medium; > + }; > + }; > + > +... > -- > 2.11.0 >
