On Tue, Jan 07, 2020 at 09:52:21AM -0800, Stephen Boyd wrote:
> Quoting Brian Masney (2020-01-07 04:03:17)
> > On Sun, Jan 05, 2020 at 12:35:33AM -0800, Stephen Boyd wrote:
> > > Quoting Brian Masney (2019-12-04 16:25:00)
> > > > +examples:
> > > > + - |
> > > > + #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
> > > > + #include <dt-bindings/gpio/gpio.h>
> > > > +
> > > > + vibrator {
> > > > + compatible = "clk-vibrator";
> > > > +
> > > > + vcc-supply = <&pm8941_l19>;
> > > > +
> > > > + clocks = <&mmcc CAMSS_GP1_CLK>;
> > > > + clock-names = "core";
> > > > + clock-frequency = <24000>;
> > > > +
> > > > + enable-gpios = <&msmgpio 60 GPIO_ACTIVE_HIGH>;
> > > > +
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&vibrator_pin>;
> > >
> > > I'm still trying to wrap my head around this. I think we can have a pwm
> > > provider in a clk controller node (so imagine &mmcc has #pwm-cells) and
> > > then this 'clk-vibrator' binding wouldn't exist? Instead we would have
> > > some sort of binding for a device that expects a pwm and whatever else
> > > is required, like the enable gpio and power supply. Is there an actual
> > > hardware block that is this way? Does it have a real product id and is
> > > made by some company? Right now this looks a little too generic to not
> > > just be a catch-all for something that buzzes.
> >
> > So have some of the Qualcomm clocks like this one register with both the
> > clk and the pwm frameworks? I feel that approach would better represent
> > the hardware in device tree.
>
> That is one option. Or another option would be to have another node that
> "adapts" a clk signal to a pwm provider. Similar to how we adapt a gpio
> to make a clk gate or mux. Something like:
>
> gcc: clock-controller@f00d {
> reg = <0xf00d 0xd00d>;
> #clock-cells = <1>;
> };
>
>
> pwm {
> compatible = "pwm-clk";
> #pwm-cells = <0>;
> clocks = <&gcc 45>;
> assigned-clocks = <&gcc 45>;
> assigned-clock-rates = <1400000>;
> };
>
> And then the pwm-clk driver would adjust the duty cycle to generate a
> pwm.
OK, that makes sense.
I'll pick this up after someone from Qualcomm posts a patch that
implements the clock duty cycle. I'm willing to do that work if someone
explains the relationship between the m, n, and d values on these clocks.
Brian
