Hi, Stephen
> > > + clks[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out",
> > "audio_pll1_bypass", base, 13);
> > > + clks[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out",
> > "audio_pll2_bypass", base + 0x14, 13);
> > > + clks[IMX8MP_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out",
> > "video_pll1_bypass", base + 0x28, 13);
> > > + clks[IMX8MP_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out",
> > "dram_pll_bypass", base + 0x50, 13);
> > > + clks[IMX8MP_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out",
> > "gpu_pll_bypass", base + 0x64, 11);
> > > + clks[IMX8MP_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out",
> > "vpu_pll_bypass", base + 0x74, 11);
> > > + clks[IMX8MP_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out",
> > "arm_pll_bypass", base + 0x84, 11);
> > > + clks[IMX8MP_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out",
> > "sys_pll1_bypass", base + 0x94, 11);
> > > + clks[IMX8MP_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out",
> > "sys_pll2_bypass", base + 0x104, 11);
> > > + clks[IMX8MP_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out",
> > > + "sys_pll3_bypass", base + 0x114, 11);
> >
> > Any reason why we can't get back clk_hw pointers instead and register
> > a hw based provider?
>
> Because i.MX8M series SoCs are still NOT using hw based clock
> implementation, some of the APIs are shared, like imx_clk_pll14xx() and
> imx8m_clk_composite() etc., so I think it is better to keep
> them(i.MX8MQ/i.MX8MM/i.MX8MN/i.MX8MP) aligned, and I will find a
> chance soon to do a patch series to switch all of them to hw based clock,
> does it make sense to you?
Please ignore this, I will do necessary patches together in this series to support
hw clk based provider for i.MX8M SoCs, i.MX8MP will use hw based provider,
and old i.MX8M SoCs will be handled later with separate patch.
Thanks,
Anson
