On Thu, Dec 26, 2019 at 02:45:41PM +0800, Anson Huang wrote:
> Add binding doc for i.MX8MP pinctrl driver.
>
> Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx>
> ---
> No changes.
> ---
> .../bindings/pinctrl/fsl,imx8mp-pinctrl.txt | 38 +
Please make this a DT schema.
> arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h | 931 +++++++++++++++++++++
> 2 files changed, 969 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt
> new file mode 100644
> index 0000000..619104b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt
> @@ -0,0 +1,38 @@
> +* Freescale IMX8MP IOMUX Controller
> +
> +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
> +for common binding part and usage.
> +
> +Required properties:
> +- compatible: "fsl,imx8mp-iomuxc"
> +- reg: should contain the base physical address and size of the iomuxc
> + registers.
> +
> +Required properties in sub-nodes:
> +- fsl,pins: each entry consists of 6 integers and represents the mux and config
> + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
> + input_val> are specified using a PIN_FUNC_ID macro, which can be found in
> + <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last integer CONFIG is
> + the pad setting value like pull-up on this pin. Please refer to i.MX8M Plus
> + Reference Manual for detailed CONFIG settings.
> +
> +Examples:
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> +};
> +
> +iomuxc: pinctrl@30330000 {
> + compatible = "fsl,imx8mp-iomuxc";
> + reg = <0x30330000 0x10000>;
> +
> + pinctrl_uart1: uart1grp {
In particular, define some node naming pattern that you can match on.
Perhaps "grp$" works.
> + fsl,pins = <
> + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
> + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
> + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
> + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
> + >;
> + };
> +};
