This add bindings documentation for the clock and reset unit found on
rk3188 SoCs from Rockchip.
Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
---
.../bindings/clock/rockchip,rk3188-cru.txt | 74 ++++++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
new file mode 100644
index 0000000..8165c0c
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+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
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+* Rockchip RK3188 Clock and Reset Unit
+
+The RK3188 clock controller generates and supplies clock to various controllers
+within the SoC and also implements a reset controller for SoC peripherals.
+There exist two variants of the rk3188 SoC, the rk3188 and rk3188a, with
+slight differences in the pll handling.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3188-cru" or "rockchip,rk3188a-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region. The first element should be the cru register space and the second
+ element should be the address of the GRF_SOC_STATUS register providing the
+ pll lock status.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+- rockchip,armclk-divider-table: when the frequency of the APLL is changed
+ some core divider clocks also need to be updated. These divider clocks have
+ SoC specific divider clock output requirements for a specific APLL clock
+ speeds. When APLL clock rate is changed, these divider clocks are
+ reprogrammed with pre-determined values in order to maintain the SoC
+ specific divider clock outputs. This property lists the divider values
+ for these clocks for supported APLL clock speeds.
+ The format of each entry included in the arm-frequency-table should be
+ defined as
+
+ cell #1: arm clock parent frequency
+ cell #2 ~ cell 3#: value of clock divider of core_peri and aclk_core.
+
+- #rockchip,armclk-cells: defines the number of cells in
+ rockchip,armclk-divider-table property. The value of this property depends on
+ the SoC type. For RK3188 SoCs it should be 3.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in dt-bindings/clock/rk3188-cru.h header and can be used
+in device tree sources.
+
+External clocks:
+
+The basic input clock is generated outside the SoC. It is expected that it is
+defined using standard clock bindings with a clock-output-name of "xin24m".
+
+Example: Clock controller node:
+
+ cru: cru@20000000 {
+ compatible = "rockchip,rk3188-cru";
+ reg = <0x20000000 0x1000>,
+ <0x200080ac 0x4>;
+
+ #clock-cells = <1>;
+
+ #rockchip,armclk-cells = <3>;
+ rockchip,armclk-divider-table = <1608000 2 3>,
+ <1416000 2 3>,
+ <1200000 2 3>,
+ <1008000 2 3>,
+ < 816000 2 3>,
+ < 504000 1 3>,
+ < 312000 0 1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@10124000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10124000 0x400>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ clocks = <&cru SCLK_UART0>;
+ };
--
1.9.0
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