> -----Original Message-----
> From: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx>
> Sent: 14 December 2019 07:43
> To: Yash Shah <yash.shah@xxxxxxxxxx>
> Cc: robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; Paul Walmsley ( Sifive)
> <paul.walmsley@xxxxxxxxxx>; aou@xxxxxxxxxxxxxxxxx;
> bmeng.cn@xxxxxxxxx; allison@xxxxxxxxxxx; alexios.zavras@xxxxxxxxx; Atish
> Patra <Atish.Patra@xxxxxxx>; tglx@xxxxxxxxxxxxx; Greg KH
> <gregkh@xxxxxxxxxxxxxxxxxxx>; devicetree@xxxxxxxxxxxxxxx; linux-
> riscv@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Yash Shah
> <yash.shah@xxxxxxxxxx>
> Subject: Re: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2
> cache way enabled
>
> On Mon, 09 Dec 2019 03:25:06 PST (-0800), yash.shah@xxxxxxxxxx wrote:
> > In order to determine the number of L2 cache ways enabled at runtime,
> > implement a private attribute using cache_get_priv_group() in
> > cacheinfo framework. Reading this attribute
> ("number_of_ways_enabled")
> > will return the number of enabled L2 cache ways at runtime.
> >
> > Signed-off-by: Yash Shah <yash.shah@xxxxxxxxxx>
> > ---
> > arch/riscv/include/asm/sifive_l2_cache.h | 2 ++
> > arch/riscv/kernel/cacheinfo.c | 31
> +++++++++++++++++++++++++++++++
> > drivers/soc/sifive/sifive_l2_cache.c | 5 +++++
> > 3 files changed, 38 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/sifive_l2_cache.h
> > b/arch/riscv/include/asm/sifive_l2_cache.h
> > index 04f6748..217a42f 100644
> > --- a/arch/riscv/include/asm/sifive_l2_cache.h
> > +++ b/arch/riscv/include/asm/sifive_l2_cache.h
> > @@ -10,6 +10,8 @@
> > extern int register_sifive_l2_error_notifier(struct notifier_block
> > *nb); extern int unregister_sifive_l2_error_notifier(struct
> > notifier_block *nb);
> >
> > +int sifive_l2_largest_wayenabled(void);
>
> I thought the plan was to get this stuff out of arch/riscv? It looks like it only
> got half-way done.
Are you suggesting to move this header file out of "/arch/riscv/include/asm/" to maybe "include/soc/sifive/"?
- Yash
