On Wed, 11 Dec 2019 14:45:37 +0900, Masahiro Yamada wrote: > According to the Denali NAND Flash Memory Controller User's Guide, > this IP has two reset signals. > > rst_n: reset most of FFs in the controller core > reg_rst_n: reset all FFs in the register interface, and in the > initialization sequencer > > This commit specifies those reset signals. > > It is possible to control them separately from the IP point of view > although they might be often tied up together in actual SoC integration. > > At least for the upstream platforms, Altera/Intel SOCFPGA and Socionext > UniPhier, the reset controller seems to provide only 1-bit control for > the NAND controller. If it is the case, the resets property should > reference to the same phandles for "nand" and "reg" resets, like this: > > resets = <&nand_rst>, <&nand_rst>; > reset-names = "nand", "reg"; > > Signed-off-by: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx> > --- > > Changes in v2: > - Split into two patches > > Documentation/devicetree/bindings/mtd/denali-nand.txt | 7 +++++++ > 1 file changed, 7 insertions(+) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
