Hi Arnd, On 19/12/19 5:33 pm, Arnd Bergmann wrote: > On Thu, Dec 19, 2019 at 12:54 PM Kishon Vijay Abraham I <kishon@xxxxxx> wrote: >> >> Hi Andrew, >> >> On 16/12/19 8:19 pm, Andrew Murray wrote: >>> On Mon, Dec 09, 2019 at 02:51:39PM +0530, Kishon Vijay Abraham I wrote: >>>> Certain platforms like TI's J721E allow only 32-bit register accesses. >>> >>> When I first read this I thought you meant only 32-bit accesses are allowed >>> and not other sizes (such as 64-bit). However the limitation you address >>> here is that the J721E allows only 32-bit *aligned* register accesses. >> >> It's both, it allows only 32-bit aligned accesses and the size should be >> only 32 bits. That's why I always use "readl" in the APIs below. > > In that case, can't you use the pci_generic_config_read32/write32 > functions with a cadence specific .map_bus() function? pci_generic_config_read32() is for reading configuration space registers only. The accessors I added here are for the controller IP configuration. For the configuration space access I use pci_generic_config_read32/write32()([PATCH 11/13] PCI: j721e: Add TI J721E PCIe driver). Thanks Kishon
