On 2019-12-18 07:20, Joakim Zhang wrote:
This patch adds the DT bindings for the NXP INTMUX interrupt
multiplexer
found in the i.MX8 family SoCs.
Signed-off-by: Joakim Zhang <qiangqing.zhang@xxxxxxx>
---
.../interrupt-controller/fsl,intmux.txt | 34
+++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.txt
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.txt
b/Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.txt
new file mode 100644
index 000000000000..be3c6848f36c
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.txt
@@ -0,0 +1,34 @@
+Freescale INTMUX interrupt multiplexer
+
+Required properties:
+
+- compatible: Should be:
+ - "fsl,imx-intmux"
+- reg: Physical base address and size of registers.
+- interrupts: Should contain the parent interrupt lines (up to 8)
used to
+ multiplex the input interrupts.
+- clocks: Should contain one clock for entry in clock-names.
+- clock-names:
+ - "ipg": main logic clock
+- interrupt-controller: Identifies the node as an interrupt
controller.
+- #interrupt-cells: Specifies the number of cells needed to encode
an
+ interrupt source. The value must be 1.
+
+Optional properties:
+
+- fsl,intmux_chans: The number of channels used for interrupt
source. The
+ Maximum value is 8.
+
+Example:
+
+ intmux@37400000 {
+ compatible = "fsl,imx-intmux";
+ reg = <0x37400000 0x1000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QM_CM40_IPG_CLK>;
+ clock-names = "ipg";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ fsl,intmux_chans = <1>;
+ };
+
What I don't understand is how the interrupt descriptor can indicate
which channel it is multiplexed on. The driver doesn't makes this
clear either, and I strongly suspect that it was never tested with
more than a single channel...
Thanks,
M.
--
Jazz is not dead. It just smells funny...
