On Mon, Dec 16, 2019 at 11:48:37AM +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> > > Add a YAML schema to use the host controller driver with the > eMMC PHY on Intel's Lightning Mountain SoC. > > Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> > --- > .../bindings/phy/intel,lgm-emmc-phy.yaml | 58 ++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml > new file mode 100644 > index 000000000000..a7d4224b2001 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings > + > +maintainers: > + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> > + > +description: |+ > + Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon > + node is used to reference the base address of eMMC phy registers. > + > + The eMMC PHY node should be the child of a syscon node with the > + required property: > + > + - compatible: Should be one of the following: > + "intel,lgm-syscon", "syscon" > + - reg: > + maxItems: 1 > + > +properties: > + compatible: > + const: intel,lgm-emmc-phy > + > + "#phy-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > +required: > + - "#phy-cells" > + - compatible > + - reg > + - clocks > + - clock-names Need to drop clock-names here too and in the example. > + > +examples: > + - | > + sysconf: chiptop@e0200000 { > + compatible = "intel,lgm-syscon", "syscon"; > + reg = <0xe0200000 0x100>; > + > + emmc-phy: emmc-phy@a8 { > + compatible = "intel,lgm-emmc-phy"; > + reg = <0x00a8 0x10>; > + clocks = <&emmc>; > + clock-names = "emmcclk"; > + #phy-cells = <0>; > + }; > + }; > +... > -- > 2.11.0 >