On Fri, Dec 13, 2019 at 07:10:41PM +0100, Miquel Raynal wrote: > PX30 SoCs use a single PHY shared by two display pipelines: MIPI DSI > and LVDS. In the case of the LVDS IP, document the possibility to fill > a PHY handle. > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > --- > .../devicetree/bindings/display/rockchip/rockchip-lvds.txt | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt > index aa5663a6fd42..ec7b4341cfd2 100644 > --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt > @@ -19,6 +19,9 @@ Required properties: > - rockchip,grf: phandle to the general register files syscon > - rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface > > +- phys: LVDS/DSI DPHY (px30 only) > +- phy-names: name of the PHY, should be "dphy" Should or must? Also, phy-names is optional only for px30 Maxime
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