Add the clock bindings for the X1830 Soc from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@xxxxxxxxxxxxxx>
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
---
Notes:
v1->v2:
Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@xxxxxxxx>"
to "周琰杰 (Zhou Yanjie) <zhouyanjie@xxxxxxxxxxxxxx>" because
the old mailbox is in an unstable state.
v2->v3:
Adjust order from [3/5] in v2 to [4/5] in v3.
v3->v4:
Adjust order from [4/5] in v3 to [3/4] in v4.
.../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
include/dt-bindings/clock/x1830-cgu.h | 46 ++++++++++++++++++++++
2 files changed, 47 insertions(+)
create mode 100644 include/dt-bindings/clock/x1830-cgu.h
diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
index 75598e6..74bfc57 100644
--- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
+++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
@@ -12,6 +12,7 @@ Required properties:
* ingenic,jz4770-cgu
* ingenic,jz4780-cgu
* ingenic,x1000-cgu
+ * ingenic,x1830-cgu
- reg : The address & length of the CGU registers.
- clocks : List of phandle & clock specifiers for clocks external to the CGU.
Two such external clocks should be specified - first the external crystal
diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h
new file mode 100644
index 00000000..6499170
--- /dev/null
+++ b/include/dt-bindings/clock/x1830-cgu.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,x1830-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ * - external clocks
+ * - PLLs
+ * - muxes/dividers in the order they appear in the x1830 programmers manual
+ * - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1830_CGU_H__
+
+#define X1830_CLK_EXCLK 0
+#define X1830_CLK_RTCLK 1
+#define X1830_CLK_APLL 2
+#define X1830_CLK_MPLL 3
+#define X1830_CLK_EPLL 4
+#define X1830_CLK_VPLL 5
+#define X1830_CLK_SCLKA 6
+#define X1830_CLK_CPUMUX 7
+#define X1830_CLK_CPU 8
+#define X1830_CLK_L2CACHE 9
+#define X1830_CLK_AHB0 10
+#define X1830_CLK_AHB2PMUX 11
+#define X1830_CLK_AHB2 12
+#define X1830_CLK_PCLK 13
+#define X1830_CLK_DDR 14
+#define X1830_CLK_MAC 15
+#define X1830_CLK_MSCMUX 16
+#define X1830_CLK_MSC0 17
+#define X1830_CLK_MSC1 18
+#define X1830_CLK_SSIPLL 19
+#define X1830_CLK_SSIMUX 20
+#define X1830_CLK_SSI0 21
+#define X1830_CLK_SMB0 22
+#define X1830_CLK_SMB1 23
+#define X1830_CLK_SMB2 24
+#define X1830_CLK_UART0 25
+#define X1830_CLK_UART1 26
+#define X1830_CLK_SSI1 27
+#define X1830_CLK_SFC 28
+#define X1830_CLK_PDMA 29
+
+#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
--
2.7.4
