On Tue, Dec 10, 2019 at 12:52 PM Brian Masney <masneyb@xxxxxxxxxxxxx> wrote:
> On Tue, Dec 10, 2019 at 04:47:35AM +0000, Taniya Das wrote:
> > On 12/5/2019 5:54 AM, Brian Masney wrote:
> > > I'm not sure about the relationship of the m, n, and d values,
> > > especially how the 50% duty cycle is calculated by inverting the n
> > > value, so that's why I'm saving the duty cycle ratio for
> > > get_duty_cycle().
(...)
> > > +static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
> > > +{
> > > + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
> > > + int ret, d_reg_val, mask;
> > > +
> > > + mask = BIT(rcg->mnd_width - 1) - 1;
> > > + d_reg_val = mask - (((mask - 17) * duty->num) / duty->den);
> > > + ret = __clk_rcg2_configure_with_duty_cycle(rcg, rcg->freq_tbl,
> > > + d_reg_val, duty->num,
> > > + duty->den);
> >
> > The duty-cycle calculation is not accurate.
> > There is already a plan to submit the duty-cycle changes from my side.
>
> OK... I assume that the m and n values need to be changed as well. I
> couldn't find any docs online about the meaning of the m, n, and d
> values and how they relate to each other.
I have also at times struggled to understand this.
If someone could just in a very concise form describe how these
rcg[2] clock dividers work and how m,n,d work that'd be GREAT.
ASCII art etc would be a bonus :)
Like with a patch with a big comment in
drivers/clk/qcom/clk-rcg.h
As these tend to be quite regularly reused and incarnated in
ever new silicon a complete picture for developers would be
much appreciated.
Yours,
Linus Walleij
