On 05. 12. 19 7:35, Rajan Vaja wrote: > ZynqMP clock driver can be used for Versal platform also. Add support > for Versal platform in ZynqMP clock driver. > > Also this patch series fixes divider calculation and adds support for get > maximum divider, clock with CLK_DIVIDER_POWER_OF_TWO flag and warn user if > clock users are more than allowed. > > Rajan Vaja (5): > dt-bindings: clock: Add bindings for versal clock driver > clk: zynqmp: Extend driver for versal > clk: zynqmp: Warn user if clock user are more than allowed > clk: zynqmp: Add support for get max divider > clk: zynqmp: Fix divider calculation > > Tejas Patel (1): > clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag > > .../devicetree/bindings/clock/xlnx,versal-clk.yaml | 64 +++++++++++ > drivers/clk/zynqmp/clkc.c | 3 +- > drivers/clk/zynqmp/divider.c | 118 +++++++++++++++++++- > drivers/clk/zynqmp/pll.c | 6 +- > drivers/firmware/xilinx/zynqmp.c | 2 + > include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++ > include/linux/firmware/xlnx-zynqmp.h | 2 + > 7 files changed, 310 insertions(+), 8 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml > create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h > That firmware changes looks good. That's why feel free to add my Acked-by: Michal Simek <michal.simek@xxxxxxxxxx> to that patches. If you want me to take it via my tree please let me know. Thanks, Michal
