On Thu, 2019-12-05 at 17:00 +0100, Daniel Lezcano wrote: > Hi Michael, > > > On 22/11/2019 10:06, michael.kao@xxxxxxxxxxxx wrote: > > From: "michael.kao" <michael.kao@xxxxxxxxxxxx> > > > > This device node is for calculating dynamic power in mW. > > Since mt8173 has two clusters, there are two dynamic power > > coefficient as well. > > Are you sure about the values? Usually, Big is ~x4 little, here it is ~x2. Hi Daniel, I have confirmed again with our IC designer. The dynamic power coefficients are these value is right. Designer comment that it is result from different IC implement. > > > Signed-off-by: Dawei Chien <dawei.chien@xxxxxxxxxxxx> > > Signed-off-by: Michael.Kao <michael.kao@xxxxxxxxxxxx> > > > > --- > > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > > index 15f1842f6df3..b03ca5a71338 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > > @@ -157,6 +157,7 @@ > > enable-method = "psci"; > > cpu-idle-states = <&CPU_SLEEP_0>; > > #cooling-cells = <2>; > > + dynamic-power-coefficient = <263>; > > clocks = <&infracfg CLK_INFRA_CA53SEL>, > > <&apmixedsys CLK_APMIXED_MAINPLL>; > > clock-names = "cpu", "intermediate"; > > @@ -170,6 +171,7 @@ > > enable-method = "psci"; > > cpu-idle-states = <&CPU_SLEEP_0>; > > #cooling-cells = <2>; > > + dynamic-power-coefficient = <263>; > > clocks = <&infracfg CLK_INFRA_CA53SEL>, > > <&apmixedsys CLK_APMIXED_MAINPLL>; > > clock-names = "cpu", "intermediate"; > > @@ -183,6 +185,7 @@ > > enable-method = "psci"; > > cpu-idle-states = <&CPU_SLEEP_0>; > > #cooling-cells = <2>; > > + dynamic-power-coefficient = <530>; > > clocks = <&infracfg CLK_INFRA_CA72SEL>, > > <&apmixedsys CLK_APMIXED_MAINPLL>; > > clock-names = "cpu", "intermediate"; > > @@ -196,6 +199,7 @@ > > enable-method = "psci"; > > cpu-idle-states = <&CPU_SLEEP_0>; > > #cooling-cells = <2>; > > + dynamic-power-coefficient = <530>; > > clocks = <&infracfg CLK_INFRA_CA72SEL>, > > <&apmixedsys CLK_APMIXED_MAINPLL>; > > clock-names = "cpu", "intermediate"; > > > >
