Hi Kishon, On 28/10/2019 12:21, Roger Quadros wrote:
Hi, On J721e platform, the 2 lanes of SERDES PHY are used to achieve USB Type-C plug flip support without any additional MUX component by using a lane swap feature. However, the driver needs to know the Type-C plug orientation before it can decide whether to swap the lanes or not. This is achieved via a GPIO named DIR. Another constraint is that the lane swap must happen only when the PHY is in inactive state. This is achieved by sampling the GPIO and programming the lane swap before bringing the PHY out of reset. This series adds support to read the GPIO and accordingly program the Lane swap for Type-C plug flip support. Series must be applied on top of https://lkml.org/lkml/2019/10/23/589
I just tested this on top of Sierra PHY patches v3 https://lkml.org/lkml/2019/11/28/186 on v5.5-rc1 USB3 works fine on J7ES. Please queue this along with the Sierra PHY patches for -next. Thanks. cheers, -roger
cheers, -roger Changelog: v4 - fixes in dt-binding document - fix typo - change to typec-dir-debounce-ms and add min/max/default values - drop reference to uint32 type - fixes in driver - change to updated typec-dir-debounce-ms property - add limit checks and use default value if not specified v3 - Rebase on v2 of PHY series and update DT binding to yaml v2 - revise commit log of patch 1 - use regmap_field in patch 3 Roger Quadros (3): phy: cadence: Sierra: add phy_reset hook dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO phy: ti: j721e-wiz: Manage typec-gpio-dir .../bindings/phy/ti,phy-j721e-wiz.yaml | 17 ++++++ drivers/phy/cadence/phy-cadence-sierra.c | 10 +++ drivers/phy/ti/phy-j721e-wiz.c | 61 +++++++++++++++++++ 3 files changed, 88 insertions(+)
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