We've always seen intermittent resets of msm8996 during boot, seemingly related to PCIe somehow. The likely cause of these errors are the fact that the CLKREF of all PHYs are parented by LN_BB, which while being on during boot is disabled by the UFS host driver if it fails to find its PHY. As such, depending on the timeing (and success) of the UFS initialization PCIe might loose its clocking. These two patches ensures that LN_BB, connected to the CXO2 pad on the SoC, is described as parent for all the CLKREF clocks. So that they all vote for this clock appropriately. Bjorn Andersson (2): clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks arm64: dts: qcom: msm8996: Define parent clocks for gcc .../devicetree/bindings/clock/qcom,gcc.yaml | 6 ++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 ++ drivers/clk/qcom/gcc-msm8996.c | 35 +++++++++++++++---- 3 files changed, 35 insertions(+), 9 deletions(-) -- 2.24.0
