On Thu, Dec 05, 2019 at 03:26:52PM +0800, Wen He wrote: > LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display > output interface. Add a YAML schema for this. > > Signed-off-by: Wen He <wen.he_1@xxxxxxx> > Signed-off-by: Michael Walle <michael@xxxxxxxx> > --- > change in v11: > - renamed 'vco-frequency' to 'fsl,vco-hz' to clearly feild definiation > > .../devicetree/bindings/clock/fsl,plldig.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.yaml > > diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml > new file mode 100644 > index 000000000000..23cce65b3a93 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bindings/clock/fsl,plldig.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding > + > +maintainers: > + - Wen He <wen.he_1@xxxxxxx> > + > +description: | > + NXP LS1028A has a clock domain PXLCLK0 used for the Display output > + interface in the display core, as implemented in TSMC CLN28HPM PLL. > + which generate and offers pixel clocks to Display. > + > +properties: > + compatible: > + const: fsl,ls1028a-plldig > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 0 > + > + fsl,vco-hz: > + $ref: '/schemas/types.yaml#/definitions/uint32' Drop this as '*-hz' already has a type. With that, Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > + description: Optional for VCO frequency of the PLL in Hertz. > + The VCO frequency of this PLL cannot be changed during runtime > + only at startup. Therefore, the output frequencies are very > + limited and might not even closely match the requested frequency. > + To work around this restriction the user may specify its own > + desired VCO frequency for the PLL. > + minimum: 650000000 > + maximum: 1300000000 > + default: 1188000000 > + > +required: > + - compatible > + - reg > + - clocks > + - '#clock-cells' > + > +examples: > + # Display PIXEL Clock node: > + - | > + dpclk: clock-display@f1f0000 { > + compatible = "fsl,ls1028a-plldig"; > + reg = <0x0 0xf1f0000 0x0 0xffff>; > + #clock-cells = <0>; > + clocks = <&osc_27m>; > + }; > + > +... > -- > 2.17.1 >
