On 2019-12-05 10:58 am, Andreas Färber wrote: [...]
+ arm_pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, + <&cpu3>; + };@Robin, is this single PPI interrupt better than previous single SPI?
Yes, a PPI is ideal (since it allows core to see its own local interrupt).
Is "arm,armv8-pmuv3" the correct one to use for Cortex-A55? There's no "arm,cortex-a55-pmu" binding - is that still in the works?
Hmm, I had thought that had been done already, but apparently not. Looks like it's high time for another round of event map updates for the latest Cortex and Neoverse cores, so I guess I'll add that to our backlog internally - although the PMU events should be in the public TRMs so if anyone else *did* fancy ploughing through them to spin patches they're always welcome to :)
In the meantime the generic PMUv3 compatible will at least expose the subset of mandatory architectural events, which is arguably more useful than nothing.
+ + psci { + compatible = "arm,psci-1.0";@Lorenzo: Same question as left unanswered for RTD1619: Should this be "arm,psci-1.0", "arm-psci-0.2"? The YAML schema allows both, without clearly documenting which one shall be used in new DTs, and there's no psci-1.0 example either.
FWIW the age of the DT shouldn't really be relevant - it's a question of whether the platform's EL3 firmware actually implements the PSCI 1.0 (or later) spec, or is some fossilised binary based on the older version.
Robin.
