> -----Original Message-----
> From: Adam Ford <aford173@xxxxxxxxx>
> Sent: Thursday, December 5, 2019 10:19 AM
> To: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Cc: Adam Ford <aford173@xxxxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>;
> Mark Rutland <mark.rutland@xxxxxxx>; Shawn Guo
> <shawnguo@xxxxxxxxxx>; Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>;
> Pengutronix Kernel Team <kernel@xxxxxxxxxxxxxx>; Fabio Estevam
> <festevam@xxxxxxxxx>; dl-linux-imx <linux-imx@xxxxxxx>;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Subject: [PATCH 5/7] arm64: dts: imx8mm: add GPC power domains
>
> There is a power domain controller on the i.XM8M Mini used for handling
> interrupts and controlling certain peripherals like USB OTG and PCIe, which
> are currently unavailable.
>
> This patch enables support the controller itself to the help facilitate enabling
> additional peripherals.
>
> Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 82
> ++++++++++++++++++++++-
> 1 file changed, 81 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 23c8fad7932b..d05c5b617a4d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include <dt-bindings/clock/imx8mm-clock.h>
> +#include <dt-bindings/power/imx8m-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -13,7 +14,7 @@
>
> / {
> compatible = "fsl,imx8mm";
> - interrupt-parent = <&gic>;
> + interrupt-parent = <&gpc>;
NACK, for imx8mm, imx8mn & future i.MX8M SOC, we don't treat GPC as interrupt controller in linux anymore.
Above change will break the low power mode support(suspend/resume)
BR
Jacky Bai
> #address-cells = <2>;
> #size-cells = <2>;
>
> @@ -495,6 +496,85 @@
> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> #reset-cells = <1>;
> };
> +
> + gpc: gpc@303a0000 {
> + compatible = "fsl,imx8mm-gpc";
> + reg = <0x303a0000 0x10000>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + pgc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pgc_mipi: power-domain@0 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_MIPI>;
> + };
> +
> + pgc_pcie: power-domain@1 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_PCIE>;
> + };
> +
> + pgc_otg1: power-domain@2 {
> + #power-domain-cells = <0>;
> + reg =
> <IMX8MM_POWER_DOMAIN_USB_OTG1>;
> + };
> +
> + pgc_otg2: power-domain@3 {
> + #power-domain-cells = <0>;
> + reg =
> <IMX8MM_POWER_DOMAIN_USB_OTG2>;
> + };
> +
> + pgc_ddr1: power-domain@4 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_DDR1>;
> + };
> +
> + pgc_gpu2d: power-domain@5 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_GPU2D>;
> + };
> +
> + pgc_gpu: power-domain@6 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_GPU>;
> + };
> +
> + pgc_vpu: power-domain@7 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_VPU>;
> + };
> +
> + pgc_gpu3d: power-domain@8 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_GPU3D>;
> + };
> +
> + pgc_disp: power-domain@9 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_DOMAIN_DISP>;
> + };
> +
> + pgc_vpu_g1: power-domain@a {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_VPU_G1>;
> + };
> +
> + pgc_vpu_g2: power-domain@b {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_VPU_G2>;
> + };
> +
> + pgc_vpu_h1: power-domain@c {
> + #power-domain-cells = <0>;
> + reg = <IMX8MM_POWER_VPU_H1>;
> + };
> + };
> + };
> };
>
> aips2: bus@30400000 {
> --
> 2.20.1
