PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
Cortex-A35 manual), D-cache is 4-way set associative (ARM
Cortex-A35manual).
An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
is 8-way set associative (ARM Cortex-A35 manual).
Describe all of them in the PX30 DTSI.
Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 1fd12bd09e83..0e10a224a84b 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -48,6 +48,13 @@
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
dynamic-power-coefficient = <90>;
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@@ -60,6 +67,13 @@
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
dynamic-power-coefficient = <90>;
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2>;
};
cpu2: cpu@2 {
@@ -72,6 +86,13 @@
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
dynamic-power-coefficient = <90>;
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2>;
};
cpu3: cpu@3 {
@@ -84,6 +105,13 @@
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
dynamic-power-coefficient = <90>;
operating-points-v2 = <&cpu0_opp_table>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2>;
};
idle-states {
@@ -107,6 +135,13 @@
min-residency-us = <2000>;
};
};
+
+ l2: l2-cache {
+ compatible = "cache";
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
};
cpu0_opp_table: cpu0-opp-table {
--
2.20.1
