On Tue, Nov 26, 2019 at 5:43 AM Ard Biesheuvel <ardb@xxxxxxxxxx> wrote:
>
> Add descriptions of the SMMUs that cover the SATA controller(s)
> on the AMD Seattle SOC. The CCP crypto accelerator shares its
> SMMU with the second SATA controller, which is only enabled on
> B1 silicon.
>
> Signed-off-by: Ard Biesheuvel <ardb@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts | 4 ++++
> arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts | 5 +++++
> arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 22 ++++++++++++++++++++
> 3 files changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
> index 8e341be9a399..be8db5758c94 100644
> --- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
> +++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
> @@ -60,6 +60,10 @@
> status = "ok";
> };
>
> +&sata0 {
> + iommus = <&sata0_smmu 0x0a>, <&sata0_smmu 0x0b>, <&sata0_smmu 0x1a>;
> +};
> +
> &spi0 {
> status = "ok";
> };
> diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
> index 92cef05c6b74..1661544eb0af 100644
> --- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
> +++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
> @@ -60,7 +60,12 @@
> status = "ok";
> };
>
> +&sata0 {
> + iommus = <&sata0_smmu 0x0e>, <&sata0_smmu 0x0f>, <&sata0_smmu 0x1e>;
> +};
> +
> &sata1 {
> + iommus = <&sata1_smmu 0x0e>, <&sata1_smmu 0x0f>, <&sata1_smmu 0x1e>;
> status = "ok";
> };
>
> diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
> index 7484ea695262..eac241c98ff0 100644
> --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
> +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
> @@ -83,6 +83,24 @@
> dma-coherent;
> };
>
> + sata0_smmu: smmu@e0200000 {
Nit: iommu@...
> + compatible = "arm,mmu-401";
> + reg = <0 0xe0200000 0 0x10000>;
> + #global-interrupts = <1>;
> + interrupts = <0 332 4>, <0 332 4>;
> + #iommu-cells = <1>;
> + dma-coherent;
> + };
> +
> + sata1_smmu: smmu@e0c00000 {
> + compatible = "arm,mmu-401";
> + reg = <0 0xe0c00000 0 0x10000>;
> + #global-interrupts = <1>;
> + interrupts = <0 331 4>, <0 331 4>;
> + #iommu-cells = <1>;
> + dma-coherent;
> + };
> +
> i2c0: i2c@e1000000 {
> status = "disabled";
> compatible = "snps,designware-i2c";
> @@ -201,6 +219,10 @@
> reg = <0 0xe0100000 0 0x10000>;
> interrupts = <0 3 4>;
> dma-coherent;
> + iommus = <&sata1_smmu 0x00>,
> + <&sata1_smmu 0x02>,
> + <&sata1_smmu 0x40>,
> + <&sata1_smmu 0x42>;
> };
>
> pcie0: pcie@f0000000 {
> --
> 2.17.1
>
