Document the bindings used by the Renesas SPI bus space controller.
Signed-off-by: Chris Brandt <chris.brandt@xxxxxxxxxxx>
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.../bindings/spi/spi-renesas-spibsc.txt | 48 +++++++++++++++++++
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create mode 100644 Documentation/devicetree/bindings/spi/spi-renesas-spibsc.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-renesas-spibsc.txt b/Documentation/devicetree/bindings/spi/spi-renesas-spibsc.txt
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+Renesas SPI Bus Space Controller (SPIBSC) Device Tree Bindings
+
+Otherwise referred to as the "SPI Multi I/O Bus Controller" in SoC hardware
+manuals. This controller was designed specifically for accessing SPI flash
+devices.
+
+Required properties:
+- compatible: should be an SoC-specific compatible value, followed by
+ "renesas,spibsc" as a fallback.
+ supported SoC-specific values are:
+ "renesas,r7s72100-spibsc" (RZ/A1)
+ "renesas,r7s9210-spibsc" (RZ/A2)
+- reg: should contain three register areas:
+ first for the base address of SPIBSC registers,
+ second for the direct mapping read mode
+- clocks: should contain the clock phandle/specifier pair for the module clock.
+- power-domains: should contain the power domain phandle/specifier pair.
+- #address-cells: should be 1
+- #size-cells: should be 0
+- flash: should be represented by a subnode of the SPIBSC node,
+ its "compatible" property contains "jedec,spi-nor" if SPI is used.
+
+Example:
+
+ spibsc: spi@1f800000 {
+ compatible = "renesas,r7s9210-spibsc", "renesas,spibsc";
+ reg = <0x1f800000 0x8c>, <0x20000000 0x10000000 >;
+ clocks = <&cpg CPG_MOD 83>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0000000 {
+ label = "u-boot";
+ reg = <0x00000000 0x80000>;
+ };
+ };
+ };
--
2.23.0
