On Fri, Nov 22, 2019 at 3:46 PM Leonard Crestez <leonard.crestez@xxxxxxx> wrote:
>
> This is used by the imx-ddrc devfreq driver to implement dynamic
> frequency scaling of DRAM.
>
> Support for proactive scaling via interconnect will come later. The
> high-performance bus masters which need that (display, vpu, gpu) are
> mostly not yet enabled in upstream anyway.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 18 ++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 ++++++++
> .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 ++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 ++++++++
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 24 +++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 10 ++++++++
> 6 files changed, 90 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> index 28ab17a277bb..ecf0d385c164 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> @@ -75,10 +75,28 @@
>
> &A53_0 {
> cpu-supply = <&buck2_reg>;
> };
>
> +&ddrc {
> + operating-points-v2 = <&ddrc_opp_table>;
> +
> + ddrc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-25M {
> + opp-hz = /bits/ 64 <25000000>;
> + };
> + opp-100M {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> + opp-750M {
> + opp-hz = /bits/ 64 <750000000>;
> + };
> + };
> +};
The SoC's device tree has the opp for the SoC. Since the SoC also has
the DDR controller, why not put the opp for the DDR into the SoC's
device tree set for its maximum rates. If the individual boards need
to change them, they can do it on a case-by-case basis.
As more and more people add devices based on imx8m q/m/n, I can
imaging a lot of these entries will be duplicated if they base their
design on the reference evk for their respective SoC.
> +
> &fec1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_fec1>;
> phy-mode = "rgmii-id";
> phy-handle = <ðphy0>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 6edbdfe2d0d7..3d4802375715 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -856,10 +856,20 @@
> #interrupt-cells = <3>;
> interrupt-controller;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + ddrc: memory-controller@3d400000 {
> + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "core", "pll", "alt", "apb";
> + clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
> + <&clk IMX8MM_DRAM_PLL>,
> + <&clk IMX8MM_CLK_DRAM_ALT>,
> + <&clk IMX8MM_CLK_DRAM_APB>;
> + };
> +
> ddr-pmu@3d800000 {
> compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
> reg = <0x3d800000 0x400000>;
> interrupt-parent = <&gic>;
> interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> index 071949412caf..b051c927c11e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> @@ -15,10 +15,28 @@
>
> &A53_0 {
> cpu-supply = <&buck2_reg>;
> };
>
> +&ddrc {
> + operating-points-v2 = <&ddrc_opp_table>;
> +
> + ddrc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-25M {
> + opp-hz = /bits/ 64 <25000000>;
> + };
> + opp-100M {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> + opp-600M {
> + opp-hz = /bits/ 64 <600000000>;
> + };
> + };
> +};
> +
> &i2c1 {
> pmic@4b {
> compatible = "rohm,bd71847";
> reg = <0x4b>;
> pinctrl-0 = <&pinctrl_pmic>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index e91625063f8e..3a79fdddc72b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -757,10 +757,20 @@
> #interrupt-cells = <3>;
> interrupt-controller;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + ddrc: memory-controller@3d400000 {
> + compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "core", "pll", "alt", "apb";
> + clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
> + <&clk IMX8MN_DRAM_PLL>,
> + <&clk IMX8MN_CLK_DRAM_ALT>,
> + <&clk IMX8MN_CLK_DRAM_APB>;
> + };
> +
> ddr-pmu@3d800000 {
> compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
> reg = <0x3d800000 0x400000>;
> interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index c36685916683..ee6dc5f07622 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -103,10 +103,34 @@
>
> &A53_3 {
> cpu-supply = <&buck2_reg>;
> };
>
> +&ddrc {
> + operating-points-v2 = <&ddrc_opp_table>;
> +
> + ddrc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-25M {
> + opp-hz = /bits/ 64 <25000000>;
> + };
> + opp-100M {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> + /*
> + * On imx8mq B0 PLL can't be bypassed so low bus is 166M
> + */
> + opp-166M {
> + opp-hz = /bits/ 64 <166935483>;
> + };
> + opp-800M {
> + opp-hz = /bits/ 64 <800000000>;
> + };
> + };
> +};
> +
> &fec1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_fec1>;
> phy-mode = "rgmii-id";
> phy-handle = <ðphy0>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 7f9319452b58..d1fcf9887f8b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1111,10 +1111,20 @@
> interrupt-controller;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-parent = <&gic>;
> };
>
> + ddrc: memory-controller@3d400000 {
> + compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "core", "pll", "alt", "apb";
> + clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
> + <&clk IMX8MQ_DRAM_PLL_OUT>,
> + <&clk IMX8MQ_CLK_DRAM_ALT>,
> + <&clk IMX8MQ_CLK_DRAM_APB>;
> + };
> +
> ddr-pmu@3d800000 {
> compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
> reg = <0x3d800000 0x400000>;
> interrupt-parent = <&gic>;
> interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.17.1
>
>
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