Quoting Jeffrey Hugo (2019-11-15 07:11:01) > On Fri, Nov 15, 2019 at 3:07 AM Taniya Das <tdas@xxxxxxxxxxxxxx> wrote: > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml > > new file mode 100644 > > index 0000000..c2d6243 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml > > @@ -0,0 +1,69 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Qualcomm Graphics Clock & Reset Controller Binding > > + > > +maintainers: > > + - Taniya Das <tdas@xxxxxxxxxxxxxx> > > + > > +description: | > > + Qualcomm grpahics clock control module which supports the clocks, resets and > > + power domains. > > + > > +properties: > > + compatible: > > + enum: > > + - qcom,msm8998-gpucc > > + - qcom,sdm845-gpucc > > + > > + clocks: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + - description: Board XO source > > + - description: GPLL0 source from GCC > > This is not an accurate conversion. GPLL0 was not valid for 845, and > is required for 8998. Thanks for checking Jeff. It looks like on 845 there are two gpll0 clocks going to gpucc. From gpu_cc_parent_map_0: "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src",
