Quoting Andrew Jeffery (2019-10-09 19:06:55) > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx> > --- Applied to clk-next
Quoting Andrew Jeffery (2019-10-09 19:06:55) > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx> > --- Applied to clk-next
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