From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@xxxxxxxxxx>
Support dynamic voltage and frequency scaling on qcs404.
CPUFreq will soon be superseded by Core Power Reduction (CPR, a form
of Adaptive Voltage Scaling found on some Qualcomm SoCs like the
qcs404).
Due to the CPR upstreaming already being in progress - and some
commits already merged - the following commit will need to be
reverted to enable CPUFreq support
Author: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@xxxxxxxxxx>
Date: Thu Jul 25 12:41:36 2019 +0200
cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist
Co-developed-by: Niklas Cassel <niklas.cassel@xxxxxxxxxx>
Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxxxxx>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@xxxxxxxxxx>
Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
---
Changes since v1:
-Removed incorrect newline in the middle of the cpu0 DT node.
(This extra newline must have been added by mistake, since no other
cpuX node in the same cluster had this extra newline added.)
arch/arm64/boot/dts/qcom/qcs404.dtsi | 30 ++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index ee5ecf413664..03aa80f2814a 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -42,6 +42,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU1: cpu@101 {
@@ -52,6 +55,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU2: cpu@102 {
@@ -62,6 +68,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU3: cpu@103 {
@@ -72,6 +81,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
L2_0: l2-cache {
@@ -94,6 +106,24 @@
};
};
+ cpu_opp_table: cpu-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ opp-microvolt = <1224000 1224000 1224000>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <1288000 1288000 1288000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-microvolt = <1384000 1384000 1384000>;
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-qcs404", "qcom,scm";
--
2.23.0
