On Mon, Nov 25, 2019 at 01:22:55PM +0100, Stephan Gerhold wrote:
> UART1 an be optionally used with additional CTS/RTS pins.
s/an/can, duh.
I will fix this if a v2 is needed for some reason; otherwise,
can you fix this when applying the patch?
Thanks!
> The pinctrl driver has an extra "u1ctsrts_a_1" pin group for them.
>
> Add a new pin configuration to configure them correctly if needed.
>
> Signed-off-by: Stephan Gerhold <stephan@xxxxxxxxxxx>
> ---
> arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi | 26 +++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
> index b6d0a60e9aed..e85a08ad2ea7 100644
> --- a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
> @@ -65,6 +65,32 @@
> ste,config = <&slpm_out_wkup_pdis>;
> };
> };
> +
> + u1ctsrts_a_1_default: u1ctsrts_a_1_default {
> + default_mux {
> + function = "u1";
> + groups = "u1ctsrts_a_1";
> + };
> + default_cfg1 {
> + pins = "GPIO6_AF6"; /* CTS */
> + ste,config = <&in_pu>;
> + };
> + default_cfg2 {
> + pins = "GPIO7_AG5"; /* RTS */
> + ste,config = <&out_hi>;
> + };
> + };
> +
> + u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep {
> + sleep_cfg1 {
> + pins = "GPIO6_AF6"; /* CTS */
> + ste,config = <&slpm_in_wkup_pdis>;
> + };
> + sleep_cfg2 {
> + pins = "GPIO7_AG5"; /* RTS */
> + ste,config = <&slpm_out_hi_wkup_pdis>;
> + };
> + };
> };
>
> uart2 {
> --
> 2.24.0
>
