On Wed, Nov 20, 2019 at 03:43:01PM +0800, Dilip Kota wrote: > Add support to PCIe RC controller on Intel Gateway SoCs. > PCIe controller is based of Synopsys DesignWare PCIe core. > > Intel PCIe driver requires Upconfigure support, Fast Training > Sequence and link speed configurations. So adding the respective > helper functions in the PCIe DesignWare framework. > It also programs hardware autonomous speed during speed > configuration so defining it in pci_regs.h. > +static void pcie_app_wr_mask(struct intel_pcie_port *lpp, > + u32 ofs, u32 mask, u32 val) It seems your editor is misconfigured. First line should be static void pcie_app_wr_mask(struct intel_pcie_port *lpp, u32 ofs, in case you would like to split it logically. > +static void pcie_rc_cfg_wr_mask(struct intel_pcie_port *lpp, > + u32 ofs, u32 mask, u32 val) Ditto. > + pcie_app_wr(lpp, PCIE_APP_IRNCR, PCIE_APP_IRN_INT); Extra white space. -- With Best Regards, Andy Shevchenko
