On 2019-11-14 09:17, shubhrajyoti.datta@xxxxxxxxx wrote: > From: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx> > > In case of multimaster configuration the last channel cached value is > not reliable. Basically the first processor/master does a write to the > mux and then to the intended slave, it caches the value. > Now the second processor/processor does a write to mux on another > channel and writes to another slave. > The first processor/master when it attempts to write the slave > skips the mux as it relies on the mux channel being the same as the > intended. This causes an issue. > > To fix that write always to the mux address. Thanks for your patch. However, I don't really see how this fixes anything. If you have multiple masters competing for the same mux, all bets are off and any solution not involving an out-of-band channel where the masters can coordinate will be racy, broken and dangerous. And since you need that extra channel anyway, it might as well also be used to coordinate when the cache needs to be invalidated. At the very least, all limitations needs to be carefully documented, but that does not mean that I will ever like it. In short, I'm extremely reluctant to add a kludge like this. Cheers, Peter
