On Wed, Nov 13, 2019 at 09:50:53PM -0800, Stephen Boyd wrote: > Quoting Manivannan Sadhasivam (2019-11-13 21:34:04) > > On Wed, Nov 13, 2019 at 02:21:15PM -0800, Stephen Boyd wrote: > > > Quoting Manivannan Sadhasivam (2019-10-26 04:02:46) > > > > Hello, > > > > > > > > This patchset adds common clock driver for Bitmain BM1880 SoC clock > > > > controller. The clock controller consists of gate, divider, mux > > > > and pll clocks with different compositions. Hence, the driver uses > > > > composite clock structure in place where multiple clocking units are > > > > combined together. > > > > > > > > This patchset also removes UART fixed clock and sources clocks from clock > > > > controller for Sophon Edge board where the driver has been validated. > > > > > > > > > > Are you waiting for review here? I see some kbuild reports so I assumed > > > you would fix and resend. > > > > I'll fix it but I was expecting some review from you so that I can send the > > next revision incorporating all comments. > > > > Ok. I'm glad I broke the silence then. > > Can you please resend without any dts changes? Those don't go through > clk tree. I'm the platform maintainer, so I'll take the dts changes via ARM SoC tree. > I think otherwise the patches look OK, although I was hoping > you could register clks by using the new way of specifying parents. Is > that possible? > Eventhough I'd like to do, my time is very constrained these days. So please consider merging it as it is and as I promised, I'll switch to the new way of specifying parents soon. Thanks, Mani
