Re: [PATCH v2 1/4] dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA

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On Thu, Nov 07, 2019 at 04:13:57AM +0200, Laurent Pinchart wrote:
> The ZynqMP includes the DisplayPort subsystem with its own DMA engine
> called DPDMA. The DPDMA IP comes with 6 individual channels
> (4 for display, 2 for audio). This documentation describes DT bindings
> of DPDMA.
> 
> Signed-off-by: Hyun Kwon <hyun.kwon@xxxxxxxxxx>
> Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> ---
> Changes since v1:
> 
> - Convert the DT bindings to YAML
> - Drop the DT child nodes
> ---
>  .../dma/xilinx/xlnx,zynqmp-dpdma.yaml         | 68 +++++++++++++++++++
>  MAINTAINERS                                   |  8 +++
>  include/dt-bindings/dma/xlnx-zynqmp-dpdma.h   | 16 +++++
>  3 files changed, 92 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
>  create mode 100644 include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
> 
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
> new file mode 100644
> index 000000000000..b677b2c4f302
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: GPL-2.0

For new bindings:

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

Otherwise,

Reviewed-by: Rob Herring <robh@xxxxxxxxxx>

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/xlnx,zynqmp-dpdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
> +
> +description: |
> +  These bindings describe the DMA engine included in the Xilinx ZynqMP
> +  DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
> +  channels for a video stream, 1 channel for a graphics stream, and 2 channels
> +  for an audio stream).
> +
> +maintainers:
> +  - Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> +
> +allOf:
> +  - $ref: "dma-controller.yaml#"
> +
> +properties:
> +  "#dma-cells":
> +    const: 1
> +    description: |
> +      The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
> +      for a list of channel IDs).
> +
> +  compatible:
> +    const: xlnx,zynqmp-dpdma
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    description: The AXI clock
> +    maxItems: 1
> +
> +  clock-names:
> +    const: axi_clk
> +
> +required:
> +  - "#dma-cells"
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    dma: dma-controller@fd4c0000 {
> +      compatible = "xlnx,zynqmp-dpdma";
> +      reg = <0x0 0xfd4c0000 0x0 0x1000>;
> +      interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> +      interrupt-parent = <&gic>;
> +      clocks = <&dpdma_clk>;
> +      clock-names = "axi_clk";
> +      #dma-cells = <1>;
> +    };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cba1095547fd..457b39bc2320 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17898,6 +17898,14 @@ F:	drivers/misc/Kconfig
>  F:	drivers/misc/Makefile
>  F:	include/uapi/misc/xilinx_sdfec.h
>  
> +XILINX ZYNQMP DPDMA DRIVER
> +M:	Hyun Kwon <hyun.kwon@xxxxxxxxxx>
> +M:	Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> +L:	dmaengine@xxxxxxxxxxxxxxx
> +S:	Supported
> +F:	Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
> +F:	include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
> +
>  XILLYBUS DRIVER
>  M:	Eli Billauer <eli.billauer@xxxxxxxxx>
>  L:	linux-kernel@xxxxxxxxxxxxxxx
> diff --git a/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
> new file mode 100644
> index 000000000000..3719cda5679d
> --- /dev/null
> +++ b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright 2019 Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> + */
> +
> +#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
> +#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
> +
> +#define ZYNQMP_DPDMA_VIDEO0		0
> +#define ZYNQMP_DPDMA_VIDEO1		1
> +#define ZYNQMP_DPDMA_VIDEO2		2
> +#define ZYNQMP_DPDMA_GRAPHICS		3
> +#define ZYNQMP_DPDMA_AUDIO0		4
> +#define ZYNQMP_DPDMA_AUDIO1		5
> +
> +#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */
> -- 
> Regards,
> 
> Laurent Pinchart
> 



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