Re: [PATCH v5 3/3] PCI: artpec6: Configure FTS with dwc helper function

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On 11/8/2019 6:43 PM, Andrew Murray wrote:
On Thu, Nov 07, 2019 at 09:03:46PM +0000, Jingoo Han wrote:
On 11/5/19, 10:44 PM, Dilip Kota wrote:
Utilize DesugnWare helper functions to configure Fast Training
Nitpicking: Fix typo (DesugnWare --> DesignWare)

If possible, how about the following?
Utilize DesignWare --> Use DesignWare

Best regards,
Jingoo Han

Sequence. Drop the respective code in the driver.

Signed-off-by: Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx>
With the changes suggested in this thread, you can add:

Reviewed-by: Andrew Murray <andrew.murray@xxxxxxx>
Sure.

Thanks a lot for reviewing patch and giving inputs,

Regards,
Dilip


---
  drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-------
  1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index d00252bd8fae..02d93b8c7942 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[];
  #define ACK_N_FTS_MASK			GENMASK(15, 8)
  #define ACK_N_FTS(x)			(((x) << 8) & ACK_N_FTS_MASK)
-#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0)
-#define FAST_TRAINING_SEQ(x)		(((x) << 0) & FAST_TRAINING_SEQ_MASK)
-
  /* ARTPEC-6 specific registers */
  #define PCIECFG				0x18
  #define  PCIECFG_DBG_OEN		BIT(24)
@@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
  	 * Set the Number of Fast Training Sequences that the core
  	 * advertises as its N_FTS during Gen2 or Gen3 link training.
  	 */
-	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-	val &= ~FAST_TRAINING_SEQ_MASK;
-	val |= FAST_TRAINING_SEQ(180);
-	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+	dw_pcie_link_set_n_fts(pci, 180);
  }

  static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
--
2.11.0



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