On Saturday, November 9, 2019, 4:21:51 PM CET Vladimir Oltean wrote: > On 09/11/2019, Andrew Lunn <andrew@xxxxxxx> wrote: > > On Sat, Nov 09, 2019 at 12:56:42PM +0200, Vladimir Oltean wrote: > >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1 > >> have interrupt lines connected to the shared IRQ2_B LS1021A pin. > >> > >> The interrupts are active low, but the GICv2 controller does not support > >> active-low and falling-edge interrupts, so the only mode it can be > >> configured in is rising-edge. > > > > Hi Vladimir > > > > So how does this work? The rising edge would occur after the interrupt > > handler has completed? What triggers the interrupt handler? > > > > Andrew > > > > Hi Andrew, > > I hope I am not terribly confused about this. I thought I am telling > the interrupt controller to raise an IRQ as a result of the > low-to-high transition of the electrical signal. Experimentation sure > seems to agree with me. So the IRQ is generated immediately _after_ > the PHY has left the line in open drain and it got pulled up to Vdd. It is correct GIC only supports raising edge and active-high. The IRQ[0:5] on ls1021a are a bit special though. They not directly connected to GIC, but there is an optional inverter, enabled by default. See RM for register SCFG_INTPCR. If left to default, those pins get actually active-high internally. There was a patch 2 years ago to add support for this inverter: https://lore.kernel.org/patchwork/patch/860993/ Best regards, Alexander
