On Fri, Nov 8, 2019 at 11:59 AM Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> wrote: > > From: Hyun Kwon <hyun.kwon@xxxxxxxxxx> > > The bindings describe the ZynqMP DP subsystem. They don't support the > interface with the programmable logic (FPGA) or audio yet. > > Signed-off-by: Hyun Kwon <hyun.kwon@xxxxxxxxxx> > Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > --- > Changes since v9: > > - Fix constraints on clock-names > - Document dp_apb_clk as the APB clock, not the AXI clock > > Changes since v8: > > - Convert to yaml > - Rename aclk to dp_apb_clk > --- > .../display/xlnx/xlnx,zynqmp-dpsub.yaml | 164 ++++++++++++++++++ > 1 file changed, 164 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
