Quoting Rajan Vaja (2019-11-06 23:16:52)
> Add documentation to describe Xilinx Versal clock driver
> bindings.
>
> Signed-off-by: Rajan Vaja <rajan.vaja@xxxxxxxxxx>
> Signed-off-by: Jolly Shah <jolly.shah@xxxxxxxxxx>
> Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx>
Signoff chain is all wrong. The sender should come last. Please read up
on how to submit patches to the kernel with proper SoB chains in kernel
docs. I can dig it up if you can't find it.
> ---
> .../devicetree/bindings/clock/xlnx,versal-clk.txt | 48 ++++++++
> include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++
> 2 files changed, 171 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt
> create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
>
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt
> new file mode 100644
> index 0000000..398e751
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt
Can you write this in YAML so we can validate it?
> @@ -0,0 +1,48 @@
> +--------------------------------------------------------------------------
> +Device Tree Clock bindings for the Xilinx Versal
> +--------------------------------------------------------------------------
> +The clock controller is a h/w block of Xilinx versal clock tree. It reads
> +required input clock frequencies from the devicetree and acts as clock provider
> +for all clock consumers of PS clocks.
> +
> +See clock_bindings.txt for more information on the generic clock bindings.
> +
> +Required properties:
> + - #clock-cells: Must be 1
> + - compatible: Must contain: "xlnx,versal-clk"
> + - clocks: List of clock specifiers which are external input
> + clocks to the given clock controller. Please refer
> + the next section to find the input clocks for a
> + given controller.
> + - clock-names: List of clock names which are exteral input clocks
> + to the given clock controller. Please refer to the
> + clock bindings for more details.
> +
> +Input clocks for Xilinx Versal clock controller:
> +
> +The Xilinx Versal has one primary and two alternative reference clock inputs.
> +These required clock inputs are:
> + - ref_clk
> + - alt_ref_clk
> + - pl_alt_ref_clk
> +
> +Output clocks are registered based on clock information received
> +from firmware. Output clocks indexes are mentioned in
> +include/dt-bindings/clock/xlnx-versal-clk.h.
> +
> +-------
> +Example
> +-------
> +
> +firmware {
> + versal_firmware: versal-firmware {
> + compatible = "xlnx,versal-firmware";
> + method = "smc";
> + versal_clk: clock-controller {
> + #clock-cells = <1>;
> + compatible = "xlnx,versal-clk";
> + clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
> + clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
> + };
> + };
> +};
> diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h
> new file mode 100644
> index 0000000..264d634
> --- /dev/null
> +++ b/include/dt-bindings/clock/xlnx-versal-clk.h
> @@ -0,0 +1,123 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2019 Xilinx Inc.
> + *
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_VERSAL_H
> +#define _DT_BINDINGS_CLK_VERSAL_H
> +
> +#define PMC_PLL 1
Why not start with 0?
