On 22-10-19, 22:30, Radhey Shyam Pandey wrote: > This patchset adds Xilinx AXI MCDMA IP support. The AXI MCDMA provides > high-bandwidth direct memory access between memory and AXI4-Stream target > peripherals. It supports up to 16 independent read/write channels. > > MCDMA IP supports per channel interrupt output but driver support one > interrupt per channel for simplification. IP specification/programming > sequence and register description is mentioned in PG [1]. > > The driver is tested with xilinx internal dmatest client. In end usecase > MCDMA will be used by xilinx axiethernet driver using dma API's. Applied, thanks -- ~Vinod
