Hi,
On Tue, Nov 05, 2019 at 11:06:51AM +0000, Andre Przywara wrote:
> As it was found recently, the Performance Monitoring Unit (PMU) on the
> Allwinner A64 SoC was not generating (the right) interrupts. With the
> SPI numbers from the manual the kernel did not receive any overflow
> interrupts, so perf was not happy at all.
> It turns out that the numbers were just off by 4, so the PMU interrupts
> are from 148 to 151, not from 152 to 155 as the manual describes.
>
> This was found by playing around with U-Boot, which typically does not
> use interrupts, so the GIC is fully available for experimentation:
> With *every* PPI and SPI enabled, an overflowing PMU cycle counter was
> found to set a bit in one of the GICD_ISPENDR registers, with careful
> counting this was determined to be number 148.
>
> Tested with perf record and perf top on a Pine64-LTS. Also tested with
> tasksetting to every core to confirm the assignment between IRQs and
> cores.
>
> This somewhat "revert-fixes" commit ed3e9406bcbc ("arm64: dts: allwinner:
> a64: Drop PMU node").
>
> Fixes: 34a97fcc71c2 ("arm64: dts: allwinner: a64: Add PMU node")
> Fixes: ed3e9406bcbc ("arm64: dts: allwinner: a64: Drop PMU node")
> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
Applied, thanks for figuring this out!
Maxime
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