Am 31. Oktober 2019 00:28:47 MEZ schrieb Florian Fainelli <f.fainelli@xxxxxxxxx>: >On 10/30/19 3:42 PM, Michael Walle wrote: >> Document the Atheros AR803x PHY bindings. >> >> Signed-off-by: Michael Walle <michael@xxxxxxxx> >> --- >> .../bindings/net/atheros,at803x.yaml | 58 >+++++++++++++++++++ >> include/dt-bindings/net/atheros-at803x.h | 13 +++++ >> 2 files changed, 71 insertions(+) >> create mode 100644 >Documentation/devicetree/bindings/net/atheros,at803x.yaml >> create mode 100644 include/dt-bindings/net/atheros-at803x.h >> >> diff --git >a/Documentation/devicetree/bindings/net/atheros,at803x.yaml >b/Documentation/devicetree/bindings/net/atheros,at803x.yaml >> new file mode 100644 >> index 000000000000..60500fd90fd8 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/atheros,at803x.yaml >> @@ -0,0 +1,58 @@ >> +# SPDX-License-Identifier: GPL-2.0+ >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/net/atheros,at803x.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Atheros AR803x PHY >> + >> +maintainers: >> + - TBD >> + >> +description: | >> + Bindings for Atheros AR803x PHYs >> + >> +allOf: >> + - $ref: ethernet-phy.yaml# >> + >> +properties: >> + atheros,clk-out-frequency: >> + description: Clock output frequency in Hertz. >> + enum: [ 25000000, 50000000, 62500000, 125000000 ] >> + >> + atheros,clk-out-strength: >> + description: Clock output driver strength. >> + enum: [ 0, 1, 2 ] >> + >> + atheros,keep-pll-enabled: >> + description: | >> + If set, keep the PLL enabled even if there is no link. Useful >if you >> + want to use the clock output without an ethernet link. > >This is more of a policy than a hardware description. Implementing this >has a PHY tunable, possibly as a form of auto-power down > >> + type: boolean >> + >> + atheros,rgmii-io-1v8: >> + description: | >> + The PHY supports RGMII I/O voltages of 2.5V, 1.8V and 1.5V. By >default, >> + the PHY uses a voltage of 1.5V. If this is set, the voltage >will changed >> + to 1.8V. > >will be changed? oh.. yes of course. >This looks like a possibly dangerous configuration as it really can >lead >to some good damage happening on the pins if there is an incompatible >voltage on the MAC and PHY side... of course, you have no way to tell >ahead of time other than by looking at the board schematics, lovely. correct.. although the standard mode of 1.5V has a max high voltage of 1.8V so this seems to be safe. But I guess no one has ever really though about how to really configure that safely. >Does the PHY come up in some sort of super isolatation mode by default >at least? not that I'm aware of. also.. the rgmii mode just works without any setup (apart from the delay and voltage settings) -michael
