Hi Tomer,
On Mon, 2019-10-28 at 17:54 +0200, Tomer Maimon wrote:
> Added device tree binding documentation for Nuvoton BMC
> NPCM reset controller.
>
> Signed-off-by: Tomer Maimon <tmaimon77@xxxxxxxxx>
> ---
> .../bindings/reset/nuvoton,npcm-reset.txt | 35 +++++++++++++++++++
> 1 file changed, 35 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
>
> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> new file mode 100644
> index 000000000000..94793285a2ac
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> @@ -0,0 +1,35 @@
> +Nuvoton NPCM Reset controller
> +
> +In the NPCM Reset controller boot the USB PHY, USB host
> +and USB device initialize.
Isn't this just a detail of the driver implementation?
> +Required properties:
> +- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
Is this driver expected to be reused for other SoCs?
> +- reg : specifies physical base address and size of the register.
> +- #reset-cells: must be set to 1
> +
> +Optional property:
> +- nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
> + NPCM7xx contain four software reset that represent numbers 1 to 4.
What's the difference between the four restart bits? Is this something
that has to be configured per board?
> + If 'nuvoton,sw-reset-number' is not specfied software reset is disabled.
> +
> +Example:
> + rstc: rstc@f0801000 {
> + compatible = "nuvoton,npcm750-reset";
> + reg = <0xf0801000 0x70>;
> + #reset-cells = <1>;
> + nuvoton,sw-reset-number = <2>;
> + };
> +
> +Specifying reset lines connected to IP NPCM7XX modules
> +======================================================
> +example:
> +
> + spi0: spi@..... {
> + ...
> + resets = <&rstc NPCM7XX_RESET_PSPI1>;
> + ...
> + };
> +
> +The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
regards
Philipp
