28.10.2019 17:57, Peter De Schrijver пишет: > On Wed, Oct 16, 2019 at 12:16:02AM +0300, Dmitry Osipenko wrote: >> CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports >> multiple parents and it has internal clock divider which uses clock >> skipping technique, meaning that CPU's voltage should correspond to the >> parent clock rate and not CCLK. PLLX is the main CCLK parent that provides >> clock rates above 1GHz and it has special property such that the CCLK's >> internal divider is set into bypass mode when PLLX is set as a parent for >> CCLK. >> >> This patch forks generic Super Clock into CCLK implementation which takes >> into account all CCLK specifics. The proper CCLK implementation is needed >> by the upcoming Tegra20 CPUFreq driver update that will allow to utilize >> the generic cpufreq-dt driver by moving intermediate clock handling into >> the clock driver. Note that technically this all could be squashed into >> clk-super, but result will be messier. >> >> Note that currently all CCLKLP bits are left in the clk-super.c and only >> CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult >> to move the CCLKLP bits, but CCLKLP is not used by anything in kernel >> and thus better not to touch it for now. > > .. > >> + super->reg = reg; >> + super->lock = lock; >> + super->width = 4; >> + super->flags = clk_super_flags; >> + super->frac_div.reg = reg + 4; >> + super->frac_div.shift = 16; >> + super->frac_div.width = 8; >> + super->frac_div.frac_width = 1; >> + super->frac_div.lock = lock; >> + super->frac_div.flags = TEGRA_DIVIDER_SUPER; >> + super->div_ops = &tegra_clk_frac_div_ops; >> + > > This is not right. The super clock divider is not a divider, it's a > pulse skipper. For the reference: on #tegra Peter explained to me in a more details what was meant here. Turned out that T30+ has a real CCLK divider and we won't use the pulse skipper for T20 nor for T30+, I'll update clk patches accordingly in the next revision.
