Re: [PATCH v3 5/6] arm: exynos: Add MCPM call-back functions

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On Sat, Apr 26, 2014 at 05:05:47PM +0100, Abhilash Kesavan wrote:
> Add machine-dependent MCPM call-backs for Exynos5420. These are used
> to power up/down the secondary CPUs during boot, shutdown, s2r and
> switching.
> 
> Signed-off-by: Thomas Abraham <thomas.ab@xxxxxxxxxxx>
> Signed-off-by: Inderpal Singh <inderpal.s@xxxxxxxxxxx>
> Signed-off-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
> Signed-off-by: Abhilash Kesavan <a.kesavan@xxxxxxxxxxx>
> ---
>  arch/arm/mach-exynos/Kconfig       |   8 +
>  arch/arm/mach-exynos/Makefile      |   2 +
>  arch/arm/mach-exynos/mcpm-exynos.c | 321 +++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/regs-pmu.h    |   3 +
>  4 files changed, 334 insertions(+)
>  create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c
> 
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index fc8bf18..1602abc 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -110,4 +110,12 @@ config SOC_EXYNOS5440
> 
>  endmenu
> 
> +config EXYNOS5420_MCPM
> +       bool "Exynos5420 Multi-Cluster PM support"
> +       depends on MCPM && SOC_EXYNOS5420
> +       select ARM_CCI
> +       help
> +         This is needed to provide CPU and cluster power management
> +         on Exynos5420 implementing big.LITTLE.
> +
>  endif
> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index a656dbe..01bc9b9 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -29,3 +29,5 @@ obj-$(CONFIG_ARCH_EXYNOS)     += firmware.o
> 
>  plus_sec := $(call as-instr,.arch_extension sec,+sec)
>  AFLAGS_exynos-smc.o            :=-Wa,-march=armv7-a$(plus_sec)
> +
> +obj-$(CONFIG_EXYNOS5420_MCPM)  += mcpm-exynos.o
> diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
> new file mode 100644
> index 0000000..f9977bf
> --- /dev/null
> +++ b/arch/arm/mach-exynos/mcpm-exynos.c
> @@ -0,0 +1,321 @@
> +/*
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + *
> + * arch/arm/mach-exynos/mcpm-exynos.c
> + *
> + * Based on arch/arm/mach-vexpress/dcscb.c
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/spinlock.h>
> +#include <linux/uaccess.h>
> +#include <linux/miscdevice.h>
> +#include <linux/fs.h>
> +#include <linux/delay.h>
> +#include <linux/arm-cci.h>

Alphabetical order please.

> +
> +#include <asm/mcpm.h>
> +#include <asm/cputype.h>
> +#include <asm/cp15.h>
> +
> +#include <plat/cpu.h>
> +
> +#include "regs-pmu.h"
> +#include "common.h"
> +
> +#define EXYNOS5420_CPUS_PER_CLUSTER    4
> +#define EXYNOS5420_NR_CLUSTERS         2
> +
> +/* Secondary CPU entry point */
> +#define REG_ENTRY_ADDR         (S5P_VA_SYSRAM_NS + 0x1C)
> +
> +/*
> + * The common v7_exit_coherency_flush API could not be used because of the
> + * Erratum 799270 workaround. This macro is the same as the common one (in
> + * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
> + */
> +#define exynos_v7_exit_coherency_flush(level) \
> +       asm volatile( \
> +       "stmfd  sp!, {fp, ip}\n\t"\
> +       "mrc    p15, 0, r0, c1, c0, 0   @ get SCTLR\n\t" \
> +       "bic    r0, r0, #"__stringify(CR_C)"\n\t" \
> +       "mcr    p15, 0, r0, c1, c0, 0   @ set SCTLR\n\t" \
> +       "isb\n\t"\
> +       "bl     v7_flush_dcache_"__stringify(level)"\n\t" \
> +       "clrex\n\t"\
> +       "mrc    p15, 0, r0, c1, c0, 1   @ get ACTLR\n\t" \
> +       "bic    r0, r0, #(1 << 6)       @ disable local coherency\n\t" \
> +       /* Dummy Load of a device register to avoid Erratum 799270 */ \
> +       "ldr    r4, [%0]\n\t" \
> +       "and    r4, r4, #0\n\t" \
> +       "orr    r0, r0, r4\n\t" \
> +       "mcr    p15, 0, r0, c1, c0, 1   @ set ACTLR\n\t" \
> +       "isb\n\t" \
> +       "dsb\n\t" \
> +       "ldmfd  sp!, {fp, ip}" \
> +       : \
> +       : "Ir" (S5P_INFORM0) \
> +       : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
> +         "r9", "r10", "lr", "memory")
> +

Still investigating to see if can work around errata 799270 in a
different fashion, will keep you posted.

> +/*
> + * We can't use regular spinlocks. In the switcher case, it is possible
> + * for an outbound CPU to call power_down() after its inbound counterpart
> + * is already live using the same logical CPU number which trips lockdep
> + * debugging.
> + */
> +static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
> +static int
> +cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
> +
> +static int exynos_cluster_power_control(unsigned int cluster, int enable)
> +{
> +       unsigned int tries = 100;
> +       unsigned int val = 0;
> +
> +       if (enable) {
> +               exynos_cluster_powerup(cluster);
> +               val = S5P_CORE_LOCAL_PWR_EN;
> +       } else {
> +               exynos_cluster_powerdown(cluster);
> +       }
> +
> +       /* Wait until cluster power control is applied */
> +       while (tries--) {
> +               if (exynos_cluster_power_state(cluster) == val)

Do you really need val ?

> +                       return 0;
> +
> +               cpu_relax();
> +       }
> +       pr_warn("timed out waiting for cluster %u to power %s\n", cluster,
> +               enable ? "on" : "off");
> +
> +       return -ETIMEDOUT;
> +}
> +
> +static int exynos_power_up(unsigned int cpu, unsigned int cluster)
> +{
> +       unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
> +       unsigned int err;
> +
> +       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> +       if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
> +               cluster >= EXYNOS5420_NR_CLUSTERS)
> +               return -EINVAL;
> +
> +       /*
> +        * Since this is called with IRQs enabled, and no arch_spin_lock_irq
> +        * variant exists, we need to disable IRQs manually here.
> +        */
> +       local_irq_disable();
> +       arch_spin_lock(&exynos_mcpm_lock);
> +
> +       cpu_use_count[cpu][cluster]++;
> +       if (cpu_use_count[cpu][cluster] == 1) {
> +               bool was_cluster_down =
> +                       __mcpm_cluster_state(cluster) == CLUSTER_DOWN;
> +
> +               /*
> +                * Turn on the cluster (L2/COMMON) and then power on the cores.
> +                * TODO: Turn off the clusters when all cores in the cluster
> +                * are down to achieve significant power savings.
> +                */
> +               if (was_cluster_down) {
> +                       err = exynos_cluster_power_control(cluster, 1);
> +                       if (err) {
> +                               exynos_cluster_power_control(cluster, 0);
> +                               return err;

You must not return without undoing what you should (irqs and locking).

> +                       }
> +               }
> +
> +               exynos_cpu_powerup(cpunr);
> +
> +               /* CPU should be powered up there */
> +               /* Also setup Cluster Power Sequence here */

Stale comment ?

> +       } else if (cpu_use_count[cpu][cluster] != 2) {
> +               /*
> +                * The only possible values are:
> +                * 0 = CPU down
> +                * 1 = CPU (still) up
> +                * 2 = CPU requested to be up before it had a chance
> +                *     to actually make itself down.
> +                * Any other value is a bug.
> +                */
> +               BUG();
> +       }
> +
> +       arch_spin_unlock(&exynos_mcpm_lock);
> +       local_irq_enable();
> +
> +       return 0;
> +}
> +
> +static void exynos_power_down(void)
> +{
> +       unsigned int mpidr, cpu, cluster;
> +       bool last_man = false, skip_wfi = false;
> +       unsigned int cpunr;
> +
> +       mpidr = read_cpuid_mpidr();
> +       cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> +       cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> +       cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
> +
> +       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> +       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
> +                       cluster >= EXYNOS5420_NR_CLUSTERS);
> +
> +       __mcpm_cpu_going_down(cpu, cluster);
> +
> +       arch_spin_lock(&exynos_mcpm_lock);
> +       BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
> +       cpu_use_count[cpu][cluster]--;
> +       if (cpu_use_count[cpu][cluster] == 0) {
> +               int cnt = 0, i;
> +
> +               exynos_cpu_powerdown(cpunr);
> +               for (i = 0; i < EXYNOS5420_CPUS_PER_CLUSTER; i++)
> +                       cnt += cpu_use_count[i][cluster];
> +               if (cnt == 0)
> +                       last_man = true;

		for (i = 0; i < EXYNOS5420_CPUS_PER_CLUSTER; i++)
			if (cpu_use_count[i][cluster])
				break;
		last_man = i == EXYNOS5420_CPUS_PER_CLUSTER;

and get rid of cnt.

> +       } else if (cpu_use_count[cpu][cluster] == 1) {
> +               /*
> +                * A power_up request went ahead of us.
> +                * Even if we do not want to shut this CPU down,
> +                * the caller expects a certain state as if the WFI
> +                * was aborted.  So let's continue with cache cleaning.
> +                */
> +               skip_wfi = true;
> +       } else {
> +               BUG();
> +       }
> +
> +       if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
> +               arch_spin_unlock(&exynos_mcpm_lock);
> +
> +               /* Flush all cache levels for this cluster. */
> +               exynos_v7_exit_coherency_flush(all);
> +
> +               /*
> +                * Disable cluster-level coherency by masking
> +                * incoming snoops and DVM messages:
> +                */
> +               cci_disable_port_by_cpu(mpidr);
> +
> +               __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
> +       } else {
> +               arch_spin_unlock(&exynos_mcpm_lock);
> +
> +               /* Disable and flush the local CPU cache. */
> +               exynos_v7_exit_coherency_flush(louis);
> +       }
> +
> +       __mcpm_cpu_down(cpu, cluster);
> +
> +       /* Now we are prepared for power-down, do it: */
> +       if (!skip_wfi)
> +               wfi();
> +
> +       /* Not dead at this point?  Let our caller cope. */
> +}
> +
> +static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
> +{
> +       unsigned int tries = 100;
> +       unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
> +
> +       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> +       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
> +                       cluster >= EXYNOS5420_NR_CLUSTERS);
> +
> +       /* Wait for the core state to be OFF */
> +       while (tries--) {
> +               if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
> +                       if ((exynos_cpu_power_state(cpunr) == 0))
> +                               return 0; /* success: the CPU is halted */
> +               }
> +
> +               /* Otherwise, wait and retry: */
> +               msleep(1);
> +       }
> +
> +       return -ETIMEDOUT; /* timeout */
> +}
> +
> +static const struct mcpm_platform_ops exynos_power_ops = {
> +       .power_up               = exynos_power_up,
> +       .power_down             = exynos_power_down,
> +       .power_down_finish      = exynos_power_down_finish,
> +};
> +
> +static void __init exynos_mcpm_usage_count_init(void)
> +{
> +       unsigned int mpidr, cpu, cluster;
> +
> +       mpidr = read_cpuid_mpidr();
> +       cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> +       cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> +
> +       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> +       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
> +                       cluster >= EXYNOS5420_NR_CLUSTERS);
> +
> +       cpu_use_count[cpu][cluster] = 1;
> +}
> +
> +/*
> + * Enable cluster-level coherency, in preparation for turning on the MMU.
> + */
> +static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
> +{
> +       asm volatile ("\n"
> +       "cmp    r0, #1\n"
> +       "bxne   lr\n"
> +       "b      cci_enable_port_for_self");
> +}

How many times are we going to duplicate this function before we decide
to move it to a common header ?

> +static int __init exynos_mcpm_init(void)
> +{
> +       int ret = 0;
> +
> +       if (!soc_is_exynos5420())
> +               return -ENODEV;

I do not particularly like these soc_is* stubs, but it is just a matter
of taste.

Thanks,
Lorenzo

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