On 4/28/2014 1:25 PM, Richard Cochran wrote:
On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote:
Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
With this enabled the L2 PTP is working.
L2 works fine without this bit. If this is needed for V3 hardware,
then it should have its own code variant.
okay
while at that rename TS_BIT8 to TS_TTL_NONZERO
Is this bit finally documented for am335x?
Not for am335x, but for other SoC's it s documented.
Thanks,
Richard
--
-George
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